snishizawa / libretto

Characterizer
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Sequential circuit DFF_PCPU failed #7

Open thou1940 opened 3 months ago

thou1940 commented 3 months ago

I tried to run the most the simple DFF_PCPU. It shows those 3 parameter have failed in the simulation

> I_VDD_LEAK = FAILED
> I_VSS_LEAK = FAILED
> I_IN_LEAK = FAILED
snishizawa commented 3 months ago

I guess condition of td and targ in these .meas are the same. It might be solved if you change the value of add_simulation_setup and add_simulation_hold. (Do not use auto for these situmation)

thou1940 commented 2 months ago

Thanks for the reply. I tried with it. But somehow it's not activated for the generated spice command. It still stays at tsetup =100p. I checked the char_seq script. it's like this starting from line 1238. maybe this is the problem? how could I activate the command?

` # if file is not exist, create spice file and run spice

if(not os.path.isfile(spicelis)):

if(os.path.isfile(spicelis)): targetLib.print_msg_sim("skip file: "+str(spicef)) else: with open(spicef,'w') as f: outlines = [] outlines.append("title: flop delay meas.\n") outlines.append(".option brief nopage nomod post=1 ingold=2 autostop\n") outlines.append(".inc '../"+str(targetCell.model)+"'\n") outlines.append(".inc '../"+str(targetCell.netlist)+"'\n") outlines.append(".param _vdd = '"+str(targetLib.vdd_voltage)+""+str(targetLib.voltage_mag)+"'\n") outlines.append(".param _vss = '"+str(targetLib.vss_voltage)+""+str(targetLib.voltage_mag)+"'\n") outlines.append(".param _vnw = '"+str(targetLib.nwell_voltage)+""+str(targetLib.voltage_mag)+"'\n") outlines.append(".param _vpw = '"+str(targetLib.pwell_voltage)+"*"+str(targetLib.voltage_mag)+"'\n") outlines.append(".param cap = 10f \n") outlines.append(".param slew = 100p \n") outlines.append(".param cslew = 100p \n") outlines.append(".param tunit = 100p \n") outlines.append(".param tsetup = 100p \n") outlines.append(".param thold = 100p \n") outlines.append(".param tsimendmag = 100 tranmag = 1\n") outlines.append(".param _tslew = slew \n")`