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spnadig
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GF180_GAFE_1
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opamp_powerPins exposed
#41
spnadig
closed
1 year ago
0
DRC clean macros for Caravel
#40
spnadig
closed
1 year ago
0
SAB layer for resistor DRC error
#39
njcoburn
opened
1 year ago
2
LVS gf180mcu_gnd issue.
#38
njcoburn
opened
1 year ago
0
Osc Macro OpenLane gen
#37
spnadig
closed
1 year ago
1
investigate why power is not routed
#36
proppy
opened
1 year ago
4
TopLevel_oscillator_macro: fix pins
#35
proppy
closed
1 year ago
0
Revert "TopLevel_osc Macro debug"
#34
spnadig
closed
1 year ago
0
TopLevel_osc Macro debug
#33
spnadig
closed
1 year ago
1
opamp macro with power pads
#32
spnadig
closed
1 year ago
0
correct DRC violations
#31
proppy
opened
1 year ago
14
add `Pad` contact to pads
#30
proppy
closed
1 year ago
2
OTA_2stage: make power pins more accessible
#29
proppy
closed
1 year ago
6
OTA_2stage_macro: fix macro export
#28
proppy
closed
1 year ago
0
OTA_2stage: error during lef extraction
#27
proppy
opened
1 year ago
2
added pads at macro & multi IP integration
#26
spnadig
closed
1 year ago
0
digital: tweak config
#25
proppy
closed
1 year ago
0
OTA_2stage_macro: add missing verilog blackbox
#24
proppy
closed
1 year ago
0
OTA_2stage: fix macro extraction
#23
proppy
closed
1 year ago
0
verified openLane
#22
spnadig
closed
1 year ago
0
openLane Dubug
#21
spnadig
closed
1 year ago
0
OTA_2stage: fix origin and boundary
#20
proppy
closed
1 year ago
1
adding opmap files
#19
spnadig
closed
1 year ago
0
add working inverter with documentation
#18
njcoburn
closed
1 year ago
0
ngspice live plotting
#17
spnadig
closed
1 year ago
0
fix top-level symbol
#16
proppy
opened
1 year ago
0
add top extraction script
#15
proppy
closed
1 year ago
0
extracted digital+analog
#14
spnadig
closed
1 year ago
1
TopLevel_oscillator: add abstract view verilog
#13
proppy
closed
1 year ago
0
add digital top
#12
proppy
closed
1 year ago
0
added FFT & files cleanup
#11
spnadig
closed
1 year ago
0
redo layout with no nwell and manually add LVPWELL to pass LVS and DR…
#10
spnadig
closed
1 year ago
0
add two_fets example
#9
proppy
closed
1 year ago
0
Flatten .gds file to pass LVS & DRC check in Klayout
#8
spnadig
closed
1 year ago
0
gds with DNWELL and netlist fixed with _dn to pass LVS
#7
spnadig
closed
1 year ago
0
fix lvs
#6
proppy
closed
1 year ago
1
fixes to debug LVS
#5
spnadig
closed
1 year ago
0
Inverter: add layout
#4
proppy
closed
1 year ago
0
updated to 5MHz ring_osc
#3
spnadig
closed
1 year ago
0
modifications to includes for ngspice
#2
spnadig
closed
1 year ago
0
Designs: use relative path
#1
proppy
closed
1 year ago
0