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sy2002 / QNICE-FPGA

QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.
http://qnice-fpga.com
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Investigate the speed grade issue and make sure timing closes on the Nexys 4 DDR #114

Open sy2002 opened 4 years ago

sy2002 commented 4 years ago

The Nexys 4 DDR seems to have a Xilinx XC7A100T-1CSG324C with a -1 speed grade.

Currently ISE and Vivado are configured for -3.

Setting it to -1 currently does not close timing.

MJoergen commented 4 years ago

I tried with speed grade -1 using Vivado to build for the Nexys4DDR board, and it closes timing without problem.

I've therefore updated to grade -1, and closing this issue.

sy2002 commented 3 years ago

assigning to me and note to self: document "the strange dashboard behavior" here and then assign to MJoergen