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sycuricon
/
starship
Run rocket-chip on FPGA
MIT License
60
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21
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make vlt for BOOM core failed
#21
pointerliu
closed
1 month ago
9
Verilator Version
#20
pointerliu
closed
1 month ago
3
No io
#19
zhouyangye1076
closed
6 months ago
0
build bitstream error: Left Record missing field (sys_rst)
#18
wisen
closed
6 months ago
9
Update 6.patch, change the VCC pin in comment
#17
zhouyangye1076
closed
8 months ago
0
No io
#16
zhouyangye1076
closed
8 months ago
0
Regvault
#15
zhouyangye1076
closed
8 months ago
0
add axis-mmio and no io top
#14
zhouyangye1076
closed
8 months ago
0
Regvault
#13
zhouyangye1076
closed
9 months ago
0
add qarma cache
#12
zhouyangye1076
closed
9 months ago
0
Regvault
#11
zhouyangye1076
closed
9 months ago
0
Regvault
#10
zhouyangye1076
closed
9 months ago
0
add jtag pin xdc pin
#9
zhouyangye1076
closed
9 months ago
0
verilator simulation
#8
zhouyangye1076
closed
11 months ago
1
Verilator
#7
zhouyangye1076
closed
11 months ago
1
Upgrade FPGA Flow
#6
zhouyangye1076
closed
11 months ago
0
merge Morfuzz
#5
Phantom1003
closed
11 months ago
0
Makefile
#4
zhouyangye1076
closed
11 months ago
2
Add Debug Module support?
#2
sheldon-cooper0
closed
9 months ago
3
support nexys a7 and boot debian
#1
monikerzju
opened
3 years ago
0