The motivation for writing these tools came from the EBAZ4205 project where the original Protel PCB design file was sourced.
In order to make the board approachable to the whole community, it was migrated to KiCad v6 (at the time of writing it wasn't finalized, so nightlies were used) which introduced the Altium PCB import functionality.
However, since the schematic and library files were missing, they had to be recreated from scratch - these tools automate some of the process.
Uses the internal PCB netlist to place, reference and connect schematic components, creating a schematic which generates an equivalent netlist.
The components still need to be organized by the user - this can be partially aided by the tool by providing a list on how to group components.
Altium Designer allows export of the internal PCB netlist via the Netlist Manager. It exports into the Protel netlist format, the specification for which is available in the Protel 99 SE Training Manual - Schematic Capture
The alternative would be to use the pcbnew API to extract netlist information from there, but given that the Altium importer isn't complete yet, I thought it's best we try to interpret data from the source.
KiCad will (eventually) have an API for eeschema, but at the time of writing isn't ready yet (and probably won't be for some time, as this feature was postponed to after v6). So the only way right now is to generate the schematic file directly.
Before KiCad v6, eeschema used its own SPICE-like format, documented in detail here.
Version v6 (+ nightlies as of Q2 2020) have switched to S-expression / s-expr / sexpr LISP-like data format. This format, at the time of writing, had no official documentation, so we need to look at the merge requests / sources
This is a development log, but it should give you a general idea
for each symbol that can be generated you provide a separate kicad schematic, which contains
- components matching rules, by which the symbol gets assigned - designator, footprint, value (can be wildcard, can be specific ID - 3 separate regexes basically) The first rule that matches gets used (as in firewall, so most specific rules first).
Note that footprint is usually useless - capacitors are in different sizes on the PCB, but same symbol on the sch.
the placed component + labels, from which we create
eeschema s-expr template for symbol
eeschema s-expr template for global labels (so that nets can be properly attached)
- pin_name has to match netlist pin name
- netlist gets parsed and for each component a dict of pin names to its connected nets is made
bounding box (with labels included) - this is so that the engine can place symbols without overlapping It also allows us to do various vertical / horizontal packing of symbols in the future.
if there is no match, we report an error - you check the symbol, you make the rule that matches it and let it go its merry way again
- there is also a "skip-missing" option for it to continue when no rule matches - the component is dropped Intended for testing so that you at least get something.
This tool was developed for KiCad Version: (5.99.0-8214-g099ddb1517), release build
Python 3.9+ is required due to PEP 585. It can be worked around to Python 3.7+ if required.
And while the base functionality works without dependencies, the tool relies on pyexcel for XLS/ODS component group file reading.
Pipfile was provided and can be used to set up the virtualenv
pipenv install
pipenv shell
./nl2sch.py ./ebaz4205/ebit_ad.Net ./ebaz4205/components/ ./ebaz4205/ebaz4205.kicad_sch --component-grouping ./ebaz4205/EBAZ4205_Kicad_recreation_effort__2021_01_24.ods --allow-missing-components --allow-missing-pinsCheck the files in the ./ebaz4205 directory to get an idea on how to prepare schematic components.
For viewing/editing the generated schematic, the following can help:
add a new sheet / standalone schematic and start moving symbols there (current nightly has support for cut-paste while keeping annotations)
Possibly even hack the control so that it doesn't bring up that pointless dialog and bind it to Ctrl+V.
Extracts internal footprints from the PCB and create a footprint library. Associates the PCB footprint instances with library footprints.
This is a development log, but it should give you a general idea
Do a script that both extracts + binds to created footprint (needs to do both so that the map for unreferenced - UNKNOWN - footprint can be made)
should be semi trivial to do
Do everything in a search & replace lambda - find reference, update footprint entry to (footprint "ebaz4205:R248" (layer "F.Cu")
ebaz4205 being the name of the library we are creating, R248 being the reference
parameters should be
- original pcb
- target pcb
- target footprint lib
This tool was developed for KiCad Version: (5.99.0-8214-g099ddb1517), release build
A standard Python 3 installation is required.
fplib.py ./ebaz4205/ebaz4205.kicad_pcb ./ebaz4205/ebaz4205_assoc.kicad_pcb ./ebaz4205/ebaz4205.prettyYou can use the pcbnew Tools > Update schematic from PCB to sync the footprint associations to the schematic.
Do whatever you want with it, don't blame me if/when it doesn't work.