Memory access code generation needs an overhaul

tum-ei-eda / M2-ISA-R

CoreDSL2 Parser with backend to generate simulation code for the ETISS instruction set simulator

https://tum-ei-eda.github.io/M2-ISA-R/

Apache License 2.0

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Memory access code generation needs an overhaul #18

Closed wysiwyng closed 1 year ago

wysiwyng commented 2 years ago

Currently the code for inserting memory access functions in the ETISS model is duplicated all over instruction_transform.py, this should be consolidated at one single point for ease of reading and maintenance.

wysiwyng commented 1 year ago

fixed in https://github.com/tum-ei-eda/M2-ISA-R/commit/2dcf5c794bd97a895089aba9d9580097d34ae7e5