This tool serves as a general-purpose instruction set architecture metamodel. A parser for CoreDSL and an architecture generator for the instruction set simulator ETISS are currently also provided.
Please note: M2-ISA-R is in heavy development, things might change and break without notice. Please report issues on GitHub for any problems you encounter.
pip
and venv
venv
somewhere: python -m venv <path-to-venv>
venv
: source <path-to-venv>/bin/activate
pip install git+https://github.com/tum-ei-eda/M2-ISA-R@coredsl2
venv
: python -m venv venv
venv
: source venv/bin/activate
pip install -e .
M2-ISA-R consists of 3 components, two of which are exchangeable for different needs:
Frontend -> Metamodel -> Backend
The frontend transforms a model specification into M2-ISA-R's internal architecture model. This model can then be transformed again to an output format, e.g. models for an ISS. This repo provides a CoreDSL frontend and an ETISS backend.
M2-ISA-R v2 currently ships three usable tools: Two parsers (for transforming CoreDSL 1.5 / 2 to a M2-ISA-R metamodel) and a writer (for generating ETISS architecture plugins). These are described seperately in their respective directories, TL;DR version:
coredsl2_parser path/to/input/<top_level>.core_desc
etiss_writer -s path/to/input/gen_model/<top_level>.m2isarmodel
For parsers, see m2isar/frontends/coredsl or m2isar/frontends/coredsl2. For the ETISS architecture writer, see m2isar/backends/etiss.