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tum-ei-eda / M2-ISA-R

CoreDSL2 Parser with backend to generate simulation code for the ETISS instruction set simulator
https://tum-ei-eda.github.io/M2-ISA-R/
Apache License 2.0
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GDB Register Print Support in `RISCVVGDBCore.h` #8

Closed fpedd closed 2 years ago

fpedd commented 2 years ago

As of now, M2-ISA-R does not generate any code for register printing via GDB in RISCVVGDBCore.h. It only provides a comment Further register should be added here to send data over gdbserver. Is that intended?

The ArchImpl in ETISS has the mapRegister method already implemented.

wysiwyng commented 2 years ago

This behavior is indeed intended at the moment. Several features have to be added manually to the generated models: exception behavior, MMU, decoding of variable-length instructions, endianness conversion, GDB server stuff and others. This tool's predecessor also did not generate these parts, simply because it had no way to do so. The situation has not changed very much unfortunately, although generating exception behavior is a planned feature for the future.

For your specific case, you can most likely just copy over the non-generated parts from the existing files in ETISS.