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tum-ei-eda / M2-ISA-R

CoreDSL2 Parser with backend to generate simulation code for the ETISS instruction set simulator
https://tum-ei-eda.github.io/M2-ISA-R/
Apache License 2.0
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Wrong code is generated in concatenation operation #9

Closed togulcan closed 2 years ago

togulcan commented 2 years ago

I was following the coredsl2 manual and I am having trouble using the concatenation operator during etiss code generation phase.

As an example the following behavioral model: image

is generating the following code: generated

where imm is shifted 3 times although it should have been shifted by 2.

As another example: image

is generating the following code: image

where im11 has not been shifted at all.

I am not sure if I am missing something or this is a possible bug. Do you have any idea?

neithernut commented 2 years ago

To me it looks like an issue with the determined widths of the literals involved. Specifically I remember some discussion of whether zero-width values should be allowed in CoreDSL and whether 0 actually (non-intuitively) ends up having a width of zero. Which would explain at least the second issue you reported.

I assume the issue goes away if you explicitly specify the literals' widths?

wysiwyng commented 2 years ago

As @neithernut suggested, M2-ISA-R infers the bit width of int literals from their value. For a specification on how that should work see here: https://github.com/Minres/CoreDSL/wiki/Literals. TLDR: Except for Verilog-style literals, bit width of a literal = the smallest size needed to represent it completely.

In your specific case, 0 being identified as being of width 0 is an error in M2-ISA-R, I will correct that. 00 on the other hand is being interpreted as an octal 0 (0 being the prefix for octal numbers). It is assigned a size of 3, which is also not in line with the CoreDSL specification.

To get the literals you want, please use Verilog-style notation: 1'b0 would get you an explicit 1 bit literal of value 0. Similarly for the second example use 2'b00.