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chisel2-deprecated
chisel.eecs.berkeley.edu
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Chisel3compatibilitycheck
#700
ucbjrl
closed
8 years ago
0
Bulk connects do not override bundle components
#699
colinschmidt
opened
8 years ago
4
Migrated black box to separate file
#698
da-steve101
closed
8 years ago
2
Catting a UInt of width 0 leads to strange sim results
#697
da-steve101
opened
8 years ago
1
Compilation Error when assigning from other clock
#696
da-steve101
opened
8 years ago
4
Correct signature for vcd dump methods (lacked t and reset arguments).
#695
ucbjrl
closed
8 years ago
0
(Relevant to Enum:) Uppercase identifiers assumed to be stable identifiers in extractor/unapply context
#694
sdtwigg
opened
8 years ago
0
Improve log2* functions, as with Chisel3
#693
aswaterman
closed
8 years ago
0
Testers Vec size issue: java.lang.IndexOutOfBoundsException
#692
hqjenny
opened
8 years ago
2
Added blocks for input, output, and input-output timing closure
#691
hutch31
opened
8 years ago
8
Fixed AsyncFifo so reset not tied to 0
#690
da-steve101
opened
8 years ago
4
Chisel.TestApplicationException: test application exit - exit code 139
#689
ascenium
opened
8 years ago
4
Fix memory access masking bug for nonPow2 memories
#688
ccelio
closed
8 years ago
3
do not extract a single bit wire
#687
donggyukim
closed
8 years ago
0
Warning message needed?
#686
da-steve101
opened
8 years ago
0
The <> operator and overriding
#685
da-steve101
closed
8 years ago
1
Tester observer
#684
ucbjrl
closed
8 years ago
0
Added a pokePart method to Tester
#683
JackDavidson
closed
8 years ago
4
Tester observer
#682
donggyukim
closed
8 years ago
0
Changed index literals to base 10
#681
JackDavidson
closed
8 years ago
2
Move tutorial doc to chisel-tutorial.
#680
ucbjrl
closed
8 years ago
0
Corrected bit width of indexes into wires in verilog
#679
JackDavidson
closed
8 years ago
8
C simulation left running if exception in tester
#678
da-steve101
closed
8 years ago
1
Verilog Address Widths Incorrect
#677
JackDavidson
closed
8 years ago
8
Another printf output fix
#676
ucbjrl
closed
8 years ago
0
Make Printf Cycle Accurate
#675
da-steve101
closed
8 years ago
2
Cocotb directives in Verilog backend
#674
Martoni
opened
8 years ago
2
A question on design
#673
da-steve101
closed
8 years ago
8
Width should grow when adding
#672
da-steve101
closed
8 years ago
13
Fix broken printf, newTestOutputString called multiple times
#671
da-steve101
closed
8 years ago
11
setModuleName is scary... (results in wrong Verilog)
#670
shunshou
opened
8 years ago
1
Changed Vec cloneType
#669
shunshou
opened
8 years ago
11
Invalid Reg width generation leads to bad bounds in generated Verilog
#668
ccelio
opened
8 years ago
8
Clock dividers / multiclock support
#667
shunshou
opened
8 years ago
5
Don't initialize the channels until we know how big they need to be - #665
#666
ucbjrl
closed
8 years ago
1
Segmentation fault crashing tester
#665
da-steve101
opened
8 years ago
3
make the package structure of hwiotesters in chisel2 emulate the two …
#664
ucbjrl
closed
8 years ago
0
Add expect(Bool, Boolean) methods
#663
da-steve101
closed
8 years ago
2
Have a link to the examples repository instead of the paper repository.
#662
schoeberl
closed
8 years ago
0
merge with master
#661
ucbjrl
closed
8 years ago
0
Issue startup error messages and exit Tester if application dies - #658
#660
ucbjrl
closed
8 years ago
0
Add Option types for Bundle.
#659
grebe
closed
8 years ago
0
tutorial hello asserts sim_api.h:37: channel_t::channel_t(int): Assertion `channel != ((void *) -1)' failed.
#658
timsifive
closed
8 years ago
4
Add Option types for Bundle.
#657
ucbjrl
closed
8 years ago
1
Flo/Dbl Improvements for Tester/AdvTester
#656
grebe
closed
8 years ago
0
Add Option types for Bundle.
#655
grebe
closed
8 years ago
1
Register size inference
#654
schoeberl
opened
8 years ago
12
Bump dependent package versions.
#653
ucbjrl
closed
8 years ago
0
Scalastyle - no functional changes
#652
ucbjrl
closed
8 years ago
0
Simplify argument handling for the Chisel3 TesterDriver.
#651
ucbjrl
closed
8 years ago
0
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