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ucsdsysnet
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Rosebud
Framework for FPGA-accelerated Middlebox Development
MIT License
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Cell is placed inside reconfig block
#7
hoangvm97
opened
1 year ago
1
Compile with normal flow (no partial reconfig) error
#6
hoangvm97
opened
1 year ago
0
Add RPU and interface count readbacks to the FPGA image
#5
mkhazraee
opened
1 year ago
0
Update PCIe modules to support straddling
#4
mkhazraee
opened
1 year ago
0
Testbenches insert packets at higher rate than 100Gbps per interface
#3
mkhazraee
opened
1 year ago
0
Very rarely a slot is returned to the LB which was supposed to be in LB and not the RPUs.
#2
mkhazraee
opened
1 year ago
1
Adjust when to drop packets per incoming interface for the RR scheduler
#1
mkhazraee
opened
1 year ago
1