Would be nice to have some explanation + links of hardcaml in README.md

[mithro]

I was looking at tools which interface with Yosys and came across your hardcaml-yosys project. However I was not easily able to understand what hardcaml is or why you would want to generate a netlist from yosys and import it into hardcaml.

It would be useful for new users to have some links to good resources on hardcaml and maybe one or two lines on why hardcaml and yosys go well together.

From what I can tell from some quick searching;

• hardcaml is an open source domain specific language embedded in OCaml for designing and testing register transfer level hardware designs.
• OCaml is a functional programming language which has a strong focus on performance.
• In digital circuit design, register-transfer level (RTL) is a design abstraction which models a synchronous digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical operations performed on those signals.

From the looks of it you are then simulating the RTL in some way using some LLVM magic?

It feels like you might be trying to simulate hardware and using Yosys to translate Verilog designs into something that you can then parse into your hardcaml language which you are then trying to simulate quickly?

I have no idea if I'm right or not :-P

[andrewray]

Hardcaml is my replacement for Verilog or VHDL.

Hardcaml-yosys and related libraries try to make that replacement process easier, given the strong industry preference for Verilog and VHDL.

At the very core of this whole thing is I truly love OCaml as a programming language, but I also do hardware design as my day job. Hardcaml and the various tools I build around it allow me to do this.