uob-hep-pc065

Design Files for DUNE Timing System FIB (Fibre Interface Board)

Designed using Cadence DE-HDL for schematic capture and Cadence Allegro PCB for layout

Versions:

• pc065a_toplevel.cpm - first version. Not used much. Schematic at https://github.com/uob-hep-cad/uob-hep-pc065/blob/master/www/Schematics/pc065b_toplevel_14may20.pdf
• pc065b_toplevel.cpm - second version. Used for tests with AFC v4. Schematic at https://github.com/uob-hep-cad/uob-hep-pc065/blob/master/www/Schematics/pc065b_toplevel_14may20.pdf
• pc065c_fibv2_toplevel.cpm - "final" / pre-production prototype