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upscale-project
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sqed-generator
Python-based workflow to generate QED modules from ISA/architecture specifications
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QuestaSim does not allow continuous assignment to a reg found in `modify_instruction.v`
#5
eldrickm
opened
3 years ago
2
QuestaSim vlog Compiler does not allow `assume` in Verilog files
#4
eldrickm
opened
3 years ago
1
Add QED license files and headers
#3
lonsing
closed
3 years ago
0
Suggested bug fix: spurious counterexamples in ridecore demo
#2
lonsing
closed
5 years ago
0
Comments on current version
#1
lonsing
closed
5 years ago
0