Examples
にあり,これを用いてビルドし,検証する.Examples/minimum_user
にある, 最小限の C2A 実行サンプルは, S2E User for C2A Core によってエミュレーション可能である.
Examples/2nd_obc_user
にある 2nd OBC (非 MOBC) の user 部を使うことで, C2A 間通信も模擬できる.Examples/minimum_user
でテストする.Examples/2nd_obc_user
を用いる.main
: リリース版(詳細)develop
: 概ね検証された最新版(beta 機能含む)feature/*
: 開発ブランチhotfix/*
: 重大バグ修正用ブランチC2A Core の採用実績のある衛星 OBC や動作実績のあるボードの情報をまとめる.
Name | Satellite | Lead Institution | Launch / Deploy | CPU | Clock | ROM | RAM | NVRAM | Storage | Interface | Reference |
---|---|---|---|---|---|---|---|---|---|---|---|
OBC (2U) | MAGNARO (Tigris) | Inamori Lab. at Nagoya University | 2022/10/12 | STMicroelectronics STM32F4 | 90 MHz | 2 MiB internal ROM | 384 KiB internal RAM, 500 KiB external SRAM | 524 KiB MRAM, 131 KiB EEPROM | 16 GB SD card | UART, SPI, I2C, GPIO, ADC, DCMI | [^1] |
OBC (1U) | MAGNARO (Piscis) | Inamori Lab. at Nagoya University | 2022/10/12 | STMicroelectronics STM32F4 | 45 MHz | 2 MiB internal ROM | 384 KiB internal RAM, 500 KiB external SRAM | 524 KiB MRAM, 131 KiB EEPROM | 16 GB SD card | UART, SPI, I2C, GPIO, ADC, DCMI | [^1] |
MOBC | SPHERE-1 EYE | Sony Group Corporation, ISSL at the University of Tokyo | 2023/01/03 | Renesas Electronics SH-2A | 200 MHz | 2.5 MiB internal ROM | 128 KiB internal RAM, 8 MiB external SRAM | 2 MiB MRAM | 2 GiB NAND flash memory | UART (RS422, LVTTL), CCSDS (LVTTL), GPIO (LVTTL), ADC | |
AOBC | SPHERE-1 EYE | Sony Group Corporation, ISSL at the University of Tokyo | 2023/01/03 | Microchip Technology PIC32MX7 | 80 MHz | 512 KiB internal ROM | 128 KiB internal RAM | 512 KiB FRAM | None | UART (RS422, RS485, LVTTL), SPI, I2C, GPIO (LVTTL), ADC | |
TOBC | SPHERE-1 EYE | Sony Group Corporation, ISSL at the University of Tokyo | 2023/01/03 | Microchip Technology PIC32MX7 | 30 MHz | 512 KiB internal ROM | 128 KiB internal RAM | None | None | UART (LVTTL), I2C, GPIO (LVTTL), ADC | |
AOBC | OPTIMAL-1 | ArkEdge Space Inc. | 2023/01/06 | ||||||||
MOBC | ONGLAISAT | ISSL at the University of Tokyo | - | Renesas Electronics SH-2A | 200 MHz | 2.5 MiB internal ROM | 128 KiB internal RAM, 8 MiB external SRAM | 2 MiB MRAM | 2 GiB NAND flash memory | UART (RS422, LVTTL), CCSDS (LVTTL), GPIO (LVTTL), ADC | [^1] |
AOBC | ONGLAISAT | ISSL at the University of Tokyo | - | Microchip Technology PIC32MX7 | 80 MHz | 512 KiB internal ROM | 128 KiB internal RAM | 512 KiB FRAM | None | UART (RS422, RS485, LVTTL), SPI, I2C, GPIO (LVTTL), ADC | [^1] |
TOBC | ONGLAISAT | ISSL at the University of Tokyo | - | Microchip Technology PIC32MX7 | 30 MHz | 512 KiB internal ROM | 128 KiB internal RAM | None | None | UART (LVTTL), I2C, GPIO (LVTTL), ADC | [^1] |
[^1]: Ryo Suzumoto, et al. Improvement of C2A (Command-Centric Architecture) Reusability for Multiple Types of OBCs and Development of Continuous Integration Environment for Reliability of Flight Software. 33rd International Symposium on Space Technology and Science, 2022-f-58, 2022.
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