controller module design

[celery6]

See #5

This one can use multiple people contributing together

Responsible for carrying out the control loop as specified by the controller theory/design group. This includes taking in required data and outputting control data value. Components:

• The task which processes the periodic control loop
• Smth to manage when the controller is allowed to run (coast phase, no errors, etc)
• Calculation stuff

Interface:

• Controller_Update_Inputs(inputs…). Allows the previous step in the data pipeline (in this case probably state estimation) to send data + notify that new data is here
• Controller_Send_Event(event). Maybe for notifying about flight phase or other events (ex, abort)? See point below about flight phase.

Things to figure out:

• How will it receive data from other modules? Current new design: Controller provides an external interface like Controller_Update_Inputs(inputs…), which other tasks call to notify+send new data. This method internally unblock the control task. Alternative design: Controller blocks on a shared queue (this is how airbrakes controller worked). Rational for choosing the new design: it makes the internal control loop not dependent on external modules—we can test Controller by mocking the Controller_Update_Inputs() method to fake inputs as needed. With the other design, you would have to first pause other modules that might be interacting with the queue, then fake data by sending to queue. This is less flexible, and kind of not great separation of concerns cuz shared queue, which can be picky to manage.
• What does it need as inputs? What does it output?
• Manage when the controller is allowed to run. Ie., only during coast phase, and possibly other conditions?
• How to interact with Flight Phase? Should Controller poll Flight Phase, or should Flight Phase notify Controller? This has implications on testability and probably other effects. See 1st bullet about receiving data
• How will it internally manage timing? Ie, block on internal queue? Semaphore? Will it reuse data or only update on new data? This is discussion for research team too Algorithm design is being done by the theory/research team. Work closely to ensure controller designs are actually doable in C, understand and communicate limitations, restrictions, etc
• Testing? This module should definitely have unit tests, focusing on validating the calculations, esp edge cases like div by 0