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wfjm
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w11
PDP-11/70 CPU core and SoC
https://wfjm.github.io/home/w11/
GNU General Public License v3.0
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fix typo in rtl/vlib/README.md
#43
arabusov
opened
5 months ago
0
A
#42
Allikooo
opened
1 year ago
0
DEUNA: buffer chaining not implemened in backend
#41
wfjm
opened
1 year ago
1
DZ11: modem control not implemented in backend
#40
wfjm
opened
1 year ago
0
add external ram support on basys3 Implementation
#39
zzsczz
closed
1 year ago
3
I have an ARTY S7 board, I'd like to try your w11 code.
#38
itoh5588
closed
1 year ago
10
PSW changed after MMU aborts in dstw flows
#37
wfjm
closed
1 year ago
0
MMU trap delayed/lost when prefetch in s_idecode done
#36
wfjm
closed
1 year ago
1
MMU: D space used instead of I space for PC deferred specifiers
#35
wfjm
closed
2 years ago
0
MMU: ACF=1 traps on any access
#34
wfjm
closed
2 years ago
0
MMU: PDR A bit is set for every access
#33
wfjm
closed
2 years ago
0
asm-11 compiles nnn(pc) as nnn
#32
wfjm
closed
2 years ago
0
time tbrun does not report correct CPU time
#31
wfjm
opened
2 years ago
0
SimH scmd files fail on current 4.* version; only 3.* supported
#30
wfjm
closed
2 years ago
5
migrate from Travis to GitHub actions
#29
wfjm
closed
2 years ago
2
RK11: write protect action too slow
#28
wfjm
opened
5 years ago
0
CPU: no mmu trap when instruction which clears trap enable itself causes a trap
#27
wfjm
closed
1 year ago
1
CPU: MMR0 trap bit set when access aborted
#26
wfjm
closed
2 years ago
0
CPU: The AIB bit in MMU PDR register set independant of ACF field
#25
wfjm
closed
2 years ago
0
CPU: src+dst deltas summed in mmr1 if register identical
#24
wfjm
closed
2 years ago
0
CPU: several deficits in trap logic
#23
wfjm
closed
1 year ago
2
How to understand tb log
#22
iknowzxc
closed
5 years ago
3
RK11,RL11: no proper NXM check in 18bit systems
#21
wfjm
opened
5 years ago
0
DL11: output chars lost when device polling used
#20
wfjm
closed
5 years ago
1
tcl getters accessing a const reference crash with a SIGSEGV
#19
wfjm
closed
5 years ago
1
w11 clock rate limited by CACHE-to-CACHE false path
#18
wfjm
opened
5 years ago
1
Help wanted: Testing with Arty S7 appreciated
#17
wfjm
closed
2 years ago
2
Help wanted: Testing with Nexys4 DDR (or Nexys A7-100T) appreciated
#16
wfjm
closed
5 years ago
1
How to run testbench
#15
iknowzxc
closed
6 years ago
1
SEGFAULT core dump after detach; ReventLoop::RemovePollHandler() can cause race condition
#14
wfjm
closed
5 years ago
1
fx2 interface blocks for certain workloads
#13
wfjm
closed
7 years ago
1
Designs fail to build under Vivado 2016.3 and 2016.4
#12
wfjm
closed
7 years ago
1
dmscnt and dmcmon disabled in Vivado based flows
#11
wfjm
closed
7 years ago
3
Many post-synthesis simulations fail
#10
wfjm
opened
7 years ago
0
Vivado xelab sometimes extremely slow
#9
wfjm
closed
2 years ago
1
TM11 controller doesn't support odd transfer size
#8
wfjm
closed
5 years ago
1
Some exotic RH70/RP/RM features not implemented
#7
wfjm
opened
7 years ago
0
ti_rri crashes in normal rundown in very rare cases
#6
wfjm
opened
7 years ago
0
IO delays still unconstraint in Vivado
#5
wfjm
opened
7 years ago
0
rlink throughput on basys3/nexys4 limited by serial port stack round trip times
#4
wfjm
opened
7 years ago
0
Bad throughput for DL11 emulation for low speed links
#3
wfjm
closed
5 years ago
1
rlink v4 error recovery not yet implemented, will crash on error
#2
wfjm
opened
7 years ago
0
rlink command lists aren't split to fit in retransmit buffer size
#1
wfjm
opened
7 years ago
0