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xlsynth / bedrock-rtl

High quality and composable base RTL libraries in SystemVerilog
Apache License 2.0
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Simulation unit test for `br_ram_flops_1r1w` #152

Closed mgottscho closed 1 week ago

mgottscho commented 1 week ago

Test combinations of depth, width, tiling, and read latencies of 0 and 1. Testbench doesn't yet support read latency > 1.