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xlsynth / bedrock-rtl

High quality and composable base RTL libraries in Verilog
Apache License 2.0
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// Copyright 2024 The Bedrock-RTL Authors // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License.

= Bedrock-RTL

WARNING: UNDER CONSTRUCTION. Everything is broken.

High quality and composable base RTL libraries in Verilog

== Prerequisites

You need to have the following tools installed in your environment.

TODO(mgottscho): Add more as we implement more things.

== Pre-Commit Hooks

We use pre-commit hooks to enforce code quality. To install the hooks, run:

[source,shell]

pre-commit install

They should automatically run on every commit. You can also run them manually via:

[source,shell]

pre-commit run

== Testing

verilog_elab_test and verilog_lint_test rules use placeholder tools by default, so those tests will always pass unless you point at real tools. To do this, set the following Bazel action environment variables to point to executables via the --action_env flag (which you can set in your .bazelrc file for convenience):

[source,shell]

bazel test //...

== Continuous Integration

Using GitHub Actions, which currently just runs Verible lint and format tests.

== Planned Features

The following table summarizes the list of features that we plan to implement in the Bedrock-RTL library. Checked boxes already have prototype implementations, though they are not verified yet.

[cols="1,2"] |=== | Category | Description

| arb a| Basic arbiters

| cdc a| Clock-domain crossings

| counter a| Counters with the following feature combinations:

| credit a| Credit/valid flow control

| delay a| Feedforward delay pipeline registers

| ecc a| Error correcting codes

| enc a| Encoders

| err a| Errors

| fifo a| FIFO (queue) controllers with external RAM ports. Combinations of:

Additionally, FIFOs that are simple wrappers around controllers and flop-RAMs.

| flow a| Ready/valid flow control (streaming)

| macros a| Macros for inferring flip-flop registers with combinations of the following features.

Macros for SystemVerilog assertions.

| ram a| Memories

| rdc a| Reset domain crossings

| timer a| Timers

|===

== Style Guide

:lowrisc-style-guide: https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md

We aim to follow the {lowrisc-style-guide}[lowRISC Verilog Style Guide^]. We will document any exceptions here.