Use when output values are always treated as valid and must be known 0 when exiting reset.
br_delay_nr
No
No (used for assertions only)
N/A
N/A
undefined
Use when output values are always treated as valid after exiting reset, and reset can be held long enough to flush through any initial value.
br_delay_valid
valid
Yes
No
Same cycle
valid: 0, data: undefined
Use when output values are only sometimes valid.
br_delay_valid_next
valid-next
Yes
No
Next cycle
valid_next: 0, data: undefined
Use when output values are only sometimes valid, and static timing may be tight (e.g., pipelining a wide bus over a long wire distance).
br_delay_valid_next_nr
valid-next
No (used for assertions only)
N/A
Next cycle
undefined
Use when output values are only sometimes valid, static timing may be tight (e.g., pipelining a wide bus over a long wire distance), and reset can be held long enough to flush all the valid bits to 0.
Pasting a summary of these five modules:
br_delay
br_delay_nr
br_delay_valid
valid
br_delay_valid_next
valid-next
br_delay_valid_next_nr
valid-next