xlsynth / bedrock-rtl

High quality and composable base RTL libraries in SystemVerilog
Apache License 2.0
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Refactor br_flow_arb/br_flow_mux for easier verification #173

Closed zhemao-openai closed 1 day ago

zhemao-openai commented 1 week ago

Currently, the logic on top of the base arbiters for br_flow_arb and br_flow_mux variants is repeated for every arbitration policy. We should reorganize into a br_flow_arb_core and br_flow_mux_core module that just contains the additional logic so that the public facing modules can just be composed of a core module plus the specific arbiter.

zhemao-openai commented 1 day ago

Fixed by #217 and #218