xlsynth / bedrock-rtl

High quality and composable base RTL libraries in SystemVerilog
Apache License 2.0
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Refactoring br_flow_arb_* modules for reusability and timing #217

Closed zhemao-openai closed 1 day ago

zhemao-openai commented 1 day ago

Factor out the policy-independent logic br_flow_arb into br_flow_arb_core module that interfaces to the brarb*_internal module at a higher level.

Use the can_grant signal from brarb*_internal so that push_ready[i] is not combinationally dependent on push_valid[i].


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