xlsynth / bedrock-rtl

High quality and composable base RTL libraries in Verilog
Apache License 2.0
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Implement #68 feature request - reinitializable `br_counter_*` #74

Closed mgottscho closed 22 hours ago

mgottscho commented 1 day ago

Added two ports to br_counter_incr and br_counter_decr.

Implements feature request #68.