make: ./ethernet_mac_tb: Command not found

[meettaraviya]

I have Ubuntu 16.04, and have installed ghdl and its dependancies. I ran the following command: make prepare ISE_DIR=/opt/Xilinx/14.7/ISE_DS/ISE/ This works.

However trying make check gives several warnings of the form "port x of entity y is not bounded" and the following error:-

./ethernet_mac_tb --stack-max-size=20M --ieee-asserts=disable
make: ./ethernet_mac_tb: Command not found
Makefile:11: recipe for target 'check' failed
make: *** [check] Error 127

[yol]

Hi, please post the full output of make prepare and especially make check. The real problem should appear before the snippet you posted since that is only the last step.

[yol]

Also paste ghdl --version output please :)

[meettaraviya]

make prepare ISE_DIR=/opt/Xilinx/14.7/ISE_DS/ISE/ gives:-

mkdir -p ghdl/unisim ghdl/xilinxcorelib #ghdl/simprim
ghdl -i --work=unisim --workdir=ghdl/unisim --std=93c -g --ieee=synopsys -fexplicit --warn-no-vital-generic /opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/unisims/*.vhd
ghdl -i --work=unisim --workdir=ghdl/unisim --std=93c -g --ieee=synopsys -fexplicit --warn-no-vital-generic /opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/unisims/primitive/*.vhd
ghdl -i --work=XilinxCoreLib --workdir=ghdl/xilinxcorelib --std=93c -g --ieee=synopsys -fexplicit --warn-no-vital-generic /opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/*.vhd
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_1.vhd:79:1:warning: library unit "blk_mem_axi_write_wrapper_beh" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_1.vhd:127:1:warning: library unit "axi_write_wrap_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_1.vhd:444:1:warning: library unit "write_netlist" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_3.vhd" [-Wlibrary]
.
.
.
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:157:1:warning: library unit "blk_mem_axi_write_wrapper_beh" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:205:1:warning: library unit "axi_write_wrap_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:523:1:warning: library unit "write_netlist" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:549:1:warning: library unit "structure" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:1110:1:warning: library unit "blk_mem_axi_read_wrapper_beh" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:1155:1:warning: library unit "blk_mem_axi_read_wrapper_beh_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:1421:1:warning: library unit "read_netlist" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:1451:1:warning: library unit "structure" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:5610:1:warning: library unit "beh_ff_clr" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:5627:1:warning: library unit "beh_ff_clr_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:5645:1:warning: library unit "beh_ff_ce" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:5663:1:warning: library unit "beh_ff_ce_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:5683:1:warning: library unit "beh_ff_pre" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:5700:1:warning: library unit "beh_ff_pre_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:5719:1:warning: library unit "beh_muxf7" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:5732:1:warning: library unit "beh_muxf7_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:5745:1:warning: library unit "state_logic" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd:5767:1:warning: library unit "state_logic_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_3.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:153:1:warning: library unit "blk_mem_axi_write_wrapper_beh" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:201:1:warning: library unit "axi_write_wrap_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:521:1:warning: library unit "write_netlist" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:547:1:warning: library unit "structure" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:1108:1:warning: library unit "blk_mem_axi_read_wrapper_beh" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:1153:1:warning: library unit "blk_mem_axi_read_wrapper_beh_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:1419:1:warning: library unit "read_netlist" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:1449:1:warning: library unit "structure" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:5614:1:warning: library unit "beh_ff_clr" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:5631:1:warning: library unit "beh_ff_clr_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:5649:1:warning: library unit "beh_ff_ce" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:5667:1:warning: library unit "beh_ff_ce_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:5687:1:warning: library unit "beh_ff_pre" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:5704:1:warning: library unit "beh_ff_pre_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:5723:1:warning: library unit "beh_muxf7" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:5736:1:warning: library unit "beh_muxf7_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:5749:1:warning: library unit "state_logic" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd:5771:1:warning: library unit "state_logic_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V6_4.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_2.vhd:153:1:warning: library unit "blk_mem_axi_write_wrapper_beh" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_2.vhd:201:1:warning: library unit "axi_write_wrap_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_2.vhd:521:1:warning: library unit "write_netlist" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_2.vhd:547:1:warning: library unit "structure" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_2.vhd:1108:1:warning: library unit "blk_mem_axi_read_wrapper_beh" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_2.vhd:1153:1:warning: library unit "blk_mem_axi_read_wrapper_beh_arch" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd" [-Wlibrary]
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_2.vhd:1419:1:warning: library unit "read_netlist" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/BLK_MEM_GEN_V7_1.vhd" [-Wlibrary]
.
.
.
/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/prims_sim_arch_v7_0.vhd:250:1:warning: library unit "cfg_lut_beh" was also defined in file "/opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/XilinxCoreLib/prims_sim_arch_v6_0.vhd" [-Wlibrary]
#ghdl -i --work=simprim --workdir=ghdl/simprim --std=93c -g --ieee=synopsys -fexplicit --warn-no-vital-generic /opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/simprims/simprim_Vcomponents.vhd /opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/simprims/simprim_Vpackage.vhd /opt/Xilinx/14.7/ISE_DS/ISE//vhdl/src/simprims/primitive/other/*.vhd

make check gave:

make check
ghdl -i --work=ethernet_mac --workdir=ghdl --std=93c -g --ieee=synopsys -fexplicit --warn-no-vital-generic *.vhd xilinx/*.vhd test/*.vhd xilinx/ipcore_dir/ethernet_mac_tx_fifo_xilinx.vhd
ghdl -m --work=ethernet_mac --workdir=ghdl -Pghdl/unisim -Pghdl/xilinxcorelib --std=93c -g --ieee=synopsys -fexplicit --warn-no-vital-generic ethernet_mac_tb
xilinx/ipcore_dir/ethernet_mac_tx_fifo_xilinx.vhd:76:49:warning: port "backup" of entity "fifo_generator_v9_3" is not bound [-Wbinding]
xilinx/ipcore_dir/ethernet_mac_tx_fifo_xilinx.vhd:58:14:warning: (in default configuration of ethernet_mac_tx_fifo_xilinx(ethernet_mac_tx_fifo_xilinx_a)) [-Wbinding]
xilinx/ipcore_dir/ethernet_mac_tx_fifo_xilinx.vhd:76:49:warning: port "backup_marker" of entity "fifo_generator_v9_3" is not bound [-Wbinding]
xilinx/ipcore_dir/ethernet_mac_tx_fifo_xilinx.vhd:58:14:warning: (in default configuration of ethernet_mac_tx_fifo_xilinx(ethernet_mac_tx_fifo_xilinx_a)) [-Wbinding]
.
.
.
xilinx/ipcore_dir/ethernet_mac_tx_fifo_xilinx.vhd:58:14:warning: (in default configuration of ethernet_mac_tx_fifo_xilinx(ethernet_mac_tx_fifo_xilinx_a)) [-Wbinding]
./ethernet_mac_tb --stack-max-size=20M --ieee-asserts=disable
make: ./ethernet_mac_tb: Command not found
Makefile:13: recipe for target 'check' failed
make: *** [check] Error 127

[meettaraviya]

ghdl --version gives:-

GHDL 0.34-dev (2017-03-01-40-g7eb4e6f) [Dunoon edition]
 Compiled with GNAT Version: 5.4.1
 mcode code generator
Written by Tristan Gingold.

Copyright (C) 2003 - 2015 Tristan Gingold.
GHDL is free software, covered by the GNU General Public License.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Btw, I decided using Isim to simulate instead of ghdl. So I am not affected by this issue. I cannot understand how to use ethernet_with_fifos entity. It would be great if you can give a quick example.

[yol]

The mcode generator of ghdl cannot create executables, hence it did not work. I only tested with gcc backend at the time. I have fixed the Makefile to run the test directly with ghdl -r so it should work now (e34fc4f).

The ports of ethernet_with_fifos are described in https://github.com/pkerling/ethernet_mac/blob/master/README.md . For an example of usage you can take a look at https://github.com/pkerling/Chips-Demo/blob/master/source/chips_mac_adaptor.vhd . Basically, you just have two FIFOs, one for RX and one for TX that you can pass Ethernet packets to and read from. I also strongly recommend reading at least parts of chapter 4 of https://github.com/pkerling/ethernet_mac_doc/blob/master/Thesis.pdf which includes flowcharts for packet reception/transmission (fig. 4.3). Feel free to ask additional questions if you get stuck somewhere.

[meettaraviya]

Thanks for replying. I read your thesis. I am not much experienced at networks, but I wrote some code. I sonly figured out the meaning of signals starting with tx and rx, and left other signals open. Will that work?

[yol]

You will obviously have to connect the clocks and the MII ports to your Ethernet PHY. For 100 MBit Ethernet (without using MIIM) this is at the very least:

• clock_125_i and miim_clock_i to (possibly the same) 125 MHz clock
• reset_i - you might get by with just setting it to 0 for testing purposes but I have not verified it
• mac_address_i (constant)
• All ports that start with mii_ must be connected to the PHY
• speed_override_i set to SPEED_100MBPS

It is probably best if you try to get https://github.com/pkerling/ethernet_mac_test/ running on your hardware first before writing a custom application.

Also: Could you test again with make check and tell me if it works now so I can close this issue?

[yol]

No further communication, closing