zhelnio ahb_lite_sdram issues - Githubissues

zhelnio / ahb_lite_sdram

SDRAM controller for MIPSfpga+ system

MIT License

20 stars 7 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

Fix several unsafe latches and incorrect write behavior

#7 jakubcabal opened 3 years ago
0
01_AhbLiteMem.bat: why data delay after read?

#6 jackzhang1992 opened 5 years ago
0
A small bug report for "03_AhbLiteRwMaster.bat"

#5 jackzhang1992 opened 6 years ago
0
Add AHB-Lite BURST support

#4 zhelnio opened 6 years ago
1
Add CDC logic and move the SDRAM module to another clock domain

#3 zhelnio opened 6 years ago
0
Add SDRAM ports to SDC file

#2 zhelnio opened 6 years ago
0
Add out-registers to SDRAM side outputs

#1 zhelnio opened 6 years ago
0