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I noticed that firrtl lets you read from inactive enum variants using code like:
```
FIRRTL version 3.2.0
circuit test:
module test:
input clk: Clock
input a: UInt
i…
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**Type of issue**: Bug Report
**Please provide the steps to reproduce the problem:**
Chisel Version: v3.5.6
FIRRTL Version: v1.5.6
Treadle Version: v1.5.6
We ran the official tests fo…
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We are currently missing a `~(~foo)` fold opportunity. The folder for `comb.xor` exists, but is blocked when an operand is defined in another block than the xor op itself.
See: https://github.com/l…
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I introduced an interface for hardware contracts to the `verif` dialect. This should be exposed to FIRRTL so that we can access it via Chisel. Here is an idea of what is needed:
- Modules need to be…
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Consider the following FIRRTL:
```firrtl
FIRRTL version 4.0.0
circuit Top :
public module Top :
input clock : Clock
input raddr : UInt
input waddr : UInt
input wdata : UInt…
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We should add a place to document the "Rationale" for FIRRTL's design, perhaps in the spirit of MLIR's rationales: https://mlir.llvm.org/docs/Rationale/ .
This has been proposed and requested by a …
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Chisel3 compatibility layer, simple format.
[Grammar available](https://github.com/freechipsproject/firrtl/blob/master/src/main/antlr4/FIRRTL.g4)
Nic30 updated
3 years ago
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The following should be illegal, but is currently parsed:
``` firrtl
FIRRTL version 4.0.0
circuit Foo:
layer A, bind:
public module Foo:
layerblock A:
wire a: UInt
wire…
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```firrtl
FIRRTL version 4.0.0
circuit Foo: %[[
{
"class": "circt.FullResetAnnotation",
"target": "~Foo|Foo>r",
"resetType": "sync"
}
]]
public module Foo:
input c : Clock…
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```firrtl
FIRRTL version 4.0.0
circuit Foo: %[[
]]
public module Foo:
input c : Clock
input i0 : UInt
input i1 : UInt
input r : UInt
output o0 : UInt
output o1 : UI…