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Hi! First of all it's really an excellent work you've done! Instiling physical laws into HOI synthesis is really cool. May I ask when you plan to release the code:)
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
When I synthesize cv64a6 core with `cv64a6_imafdc_sv39_config_pkg.sv` with Design Compi…
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In your paper that introduces PolyVerif in IEEE Access (https://ieeexplore.ieee.org/document/10075634), you refer to test synthesis on page 28349 (page 7 of your paper): "Once simulation finds a poten…
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We could need a new kind of TVS (Topology vs. Synthesis) tool, which checks our designs (magic or GDS2) against this truthtable: https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/des…
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The Lef21 docs begin with:
> LEF is near-ubiquitously used IC-industry-wide for two related purposes:
>
> LEF design libraries, primarily comprised of LEF macros, provide the physical abstract …
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With the new VQ file (top_post_synthesis.no_split.v) supporting the bus signals, we get syntax error when compiling in the simulator:
# ** Error: D:/Tamar2/System_Engineering/AntMicro/QLSOFA/OpenFP…
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Hi Coyote Maintainers:
I am a PhD student from Northeastern University in Boston, US. I am considering using Coyote RDMA part in our project to communicate with Mellanox RDMA NIC. I am currently tr…
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In the macro placement DEF file, the macro placement status is listed as "[placed](https://github.com/TILOS-AI-Institute/MacroPlacement/blob/ebfc003d1c1e042a1050f36086362c2c571094b4/Flows/NanGate45/ar…
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Hello, after reading the [Question 1](https://tilos-ai-institute.github.io/MacroPlacement/Docs/OurProgress/#Question1) about initial set of placement locations (from physical synthesis) affect the (re…
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Hello,
I wanted to ask if there is an available way to use the OpenROAD-flow scripts and be able to transfer the LEF/DEF contents and use it for Circuit Training. So far I have been trying to use the…