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Should we block TTBR from sending if there are other delivery constraints defined to be compliant with other transports / TimeoutManager (breaking change, Major).
Given this would be a change in be…
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In the log file, there are traces of _x86_64_ notions that are not related to _aarch64_. They could be leftovers of some previous c/p with no real effect but should be removed as they cause confusion.…
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And it's seem's wrong for meltdown with krtt https://siguza.github.io/KTRR/
at el1 T1SZ is set to 25 :
first range from 0xffffff8000000000 eg:vbar_el1?
second range from 0xffffffc000000000 the re…
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While discussing TTL (Time To Live / Time To Be Received) for the SQL transport I was thinking about MSMQ its TTRQ attribute. It does not make sense to have this in the SQL transport but it does make …
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https://github.com/zhuowei/HvDecompile/blob/ab82be558c365abc92068e61901a3f0179d349eb/hv_kernel_structs.h#L370
vcpu_zone leaks when you call hv_vcpu_get_sys_reg in x9:
I am trying to get exits on V…
fozog updated
2 years ago
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**Describe the bug**
I was trying to run a baremetal arm32 binary built using picolibc, which uses prefetch (`pld [srcin, #0]`) inside strlen(). When using TimingSimpleCpu or MinorCpu, the CPU no lon…
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**Describe the system**
System name: any SoC with ID_AA64DFR0_EL1[11:8] PMUVer != 0
Vendor name: multiple
SoC name: multiple
URL to product page:
https://developer.arm.com/documentation/ddi0595/2…
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Hello, I am trying to retrieve L3 data from a trace, so I checked the documentation and found that I could query the wattson.system_state table. I used the following query:
```sql
INCLUDE PERFETTO M…
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hi,
Sometimes we need use s/w emulation for cpu power cycle, so that when the cpu enter wfi, it will not really be powered off.
For this case, s/w can let the cpu exit from cache coherency domain an…
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Hi,
My Mac crashes during validation after flashing to the SD Card. I haven’t encountered this issue before; it just started happening last week. I’m running macOS 14.1.1 Apple m1 and using BalenaE…