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### Discussed in https://github.com/konosubakonoakua/blog/discussions/7
Originally posted by **konosubakonoakua** March 12, 2024
# zynq
## Manual
- [Embedded-Design-Tutorials](https://xili…
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Hi,
Could you please let me know what maximum supported frequency of riscv in Xilinx device(like artix or virtex ultrascale, ultrascale plus)?
Thank you so much,
Duc
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cc @gussmith23
While synthesis passes the following workloads, the Verilator tasks give the following error:
```
testbench: /home/acheung8/lakeroad-evaluation/out/robustness_experiments/muladd…
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https://github.com/bespoke-silicon-group/basejump_stl/blob/321c89653f5ad7fb1236f18c3ade085e5dbbb9d3/hard/ultrascale_plus/bsg_link/README.md?plain=1#L1
Hi Paul, I noticed that we don't have the FPGA…
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Hi there,
I've been working with AntMicro's Rowhammer tester on a ZCU104 development board. This framework instantiates a DDR4 PHY with a clock frequency of 500 MHz. I was not seeing the outputs I …
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Thanks for your greate job, i hope the project to support xilinx kc705 pcie2.0.
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Hi,
Would you be open to add support for the Intel PCIe IP cores? If so, I might be able to contribute that.
Do you have any idea of how one might best integrate a new pinout and behaviour? Whil…
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I'd like to migrate a MPSoC (Ultrascale) project to 4.x, but
https://github.com/FreeRTOS/FreeRTOS-Plus-TCP/blob/main/source/portable/NetworkInterface/xilinx_ultrascale/NetworkInterface.c
is not…
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When Lakeroad is used to synthesize a design with multiple modules, `lakeroad.so` experiences a segmentation fault.
![image](https://github.com/user-attachments/assets/f3e1caaf-022e-4281-a225-98ff…
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1 solution is to move returned address to be an argument and make return value success/failure-reason