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### What's hard to do? (limit 100 words)
Currently when choosing between the DSLX interpreter, the IR interpreter, the JIT or a Verilog simulator to run a set of DSLX tests: developers have to go thr…
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It would be good to make Verilog testing independent from commercial tools - Synopsys VCS. A potential solution would be to use verilator instead.
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Hi Taichi,
I was searching for open-source AXI BFMs and landed onto your repository on github. This and your rggen is awesome piece of work and is very helpful. A big thank you to you for putting y…
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I want to run the simulation tests for this design , however I am unable to run the test with the command "make WAVES=1". I get below error.
FST warning: ignoring signals in previously scanned scop…
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Hello,
I have a very basic test bench with a vhdl top and two sub-modules: one vhdl and one verilog.
When trying to access the verilog submodule from a cocotb TB I have an error:
Unable to cr…
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Hi, just wondering if the mixedsvvh flag could potentially be removed from this line: https://github.com/themperek/cocotb-test/blob/4924adc78712434dcd076060777239c04a22bfe8/cocotb_test/simulator.py#L5…
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### What's hard to do? (limit 100 words)
Due to the lack of interactive DSLX debugger when troubleshooting a logic issue in a `fn` developers can't really introspect value of intermediate let bindi…
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Environments
```
operating system WSL Ubuntu 20.04
cocotb version 1.8.1 (installed from pip)
verilator version 5.023 devel rev v5.020-176-g953249aa4 (built from source)
python version 3.10.14…
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Getting the simulator's precision in Xcelium with VHDL toplevels is impossible currently for two reasons:
1. Xcelium does not implement the VHPI call to get the precision in VDHL: `vhpi_get_phys(v…
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Hi @MarcoIeni,
I was running VUnit using this repository as a base, combined with github actions and simple but different source code.
The simulated verification fails to compile with the code …