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This example
```python
# a.py
import magma as m
class FullAdder(m.Circuit):
io = m.IO(
a=m.In(m.Bit),
b=m.In(m.Bit),
cin=m.In(m.Bit),
sum_=m.Out(m.Bit)…
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By default, we should use a `.sv` file name if we generated ndarrays using unpacked arrays (since this is a system verilog feature). This should make it easier for downstream tools to consume the gen…
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Also do not delete any of these extensions in cullgraph.
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@jeffsetter it seems that the ROM outputs for the 1 pix / 3 cycles and 1 pix / 9 cycles coreir output is still not correct:
```bash
%Error: harris_sch4_1pp3c.v:3137:98: Too many digits for 16 bit …
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The memory abstraction that I would like for simulating my circuits is a memory where the read data appears at the same time as the read address comes in. Note that this might not be feasible in a nor…
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I am working on a magma circuit (~350 lines of code), which takes ~40 minutes to compile to mlir (not mlir-verilog, which I assume will take longer). Of course, the long compile time could also be bec…
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Not sure why this test is failing, I think I have updated everything.
```
tests/test_deprecated/test_old_io_syntax/test_old_io_syntax_define.py .F [ 20%]
=================================== F…
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Don't invent new ones until needed
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Here are some ideas for speeding up our testing:
* Use mlir-verilog by default rather than coreir-verilog. I believe this is already a goal of magma 3.0.
* Avoid compilation when possible. I.e. us…
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I am experiencing an issue where any attempts to generate a Verilog for my test bench is segfaulting.
```
%> coreir --version
v0.1.51
```
This error can be reproduced by checking out `lake:sp…