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create introduction about the project.
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I managed to convert the g29 pedal board to usb, by connecting the potentiometers directly to the stm32 board, before closing the top cover I tested it and I didn't have that kind of oscillation that …
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**[ UUID ]** 0261307c-be02-4ecf-8f99-2ceea5af8d2e
**[ Session Name ]** ExperiSensing Our World
**[ Primary Space ]** Youth Zone
**[ Secondary Space ]** Digital Inclusion
**[ Submitter's Name ]** Tu…
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Is it possible to add support for building asynchronous circuits and also provide some tutorial on how this can be done on Chisel.
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Changing the assert to LOW will fix this? This test assumes that some pins are plugged?
Details below
=================================================== FAILURES ====================================…
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We should lint attributes of the style `#[cfg(all(not(_), not(_), ..))]` and `#[cfg(any(not(_), not(_), ..))]` and suggest `#[cfg(not(any(_, _, ..))]` and `#[cfg(not(all(_, _, ..))]`, respectively. B…
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It would be great if you could be able to share chips to other users and to have a prebuild library of chips to use, so you don't start all over again.
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Hello :wave: Cool project!
I just wanted to ask what is planned for the Verilog generation in the TODO section of the README? I'm a Verilog RTL developer and would be keen to contribute to this pro…
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The bug is that
1) sometimes negate gate (NOT gate) fails in random delay mode. Note that the input is not an Error nor an Unknown, it is just 0, and output is also 0... I do not see how such state…