ucb-bar chisel2-deprecated issues

ucb-bar / chisel2-deprecated

chisel.eecs.berkeley.edu

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#750 albert-magyar closed 4 years ago
2
Issue deprecation warning on startup.

#749 ucbjrl closed 6 years ago
6
Attaching Analog(X.W) to several Analog(1.W)

#748 mwachs5 closed 6 years ago
1
Is it legal to connect empty bundles?

#747 mwachs5 closed 6 years ago
1
Update README - more prominent notice of migration to Chisel3.

#746 ucbjrl closed 6 years ago
0
documentation link is dead

#745 PeterAaser closed 2 years ago
12
Move chisel3 compatible casts {as,to}{S,U}Int from Bits to Node.

#744 ucbjrl closed 7 years ago
0
Updatedeprecated

#743 ucbjrl closed 7 years ago
0
verilator fails to compile small Example

#742 oharboe opened 7 years ago
0
Wide rom fix

#741 ucbjrl closed 7 years ago
0
unable to create a ROM with datawidth more than 64

#740 anupkini closed 7 years ago
1
libraryDependencies latest.release not found

#739 colin4124 closed 7 years ago
2
C++ output from Chisel has been dropped

#738 olofk opened 7 years ago
1
Queue is not getting synthesized

#737 preyas3359 opened 7 years ago
0
Buildinfo

#736 ucbjrl closed 7 years ago
0
Use unconventional (but consistent) package name.

#735 ucbjrl closed 7 years ago
0
Add support for Chisel3 tutorial (organization + features)

#734 ucbjrl closed 7 years ago
0
Invalid verilog generated with constant idx into ROM

#733 da-steve101 opened 7 years ago
1
Invalid verilog generated with constant idx into ROM

#732 da-steve101 closed 7 years ago
1
Allow specifying of clock for blackbox module

#731 da-steve101 opened 7 years ago
2
abstract type T in type pattern Chisel.Ex[T] is unchecked since it is eliminated by erasure

#730 drom opened 7 years ago
0
Exception: sbt.TrapExitSecurityException

#729 drom opened 7 years ago
2
Add support for new chisel3 tutorials.

#728 ucbjrl closed 7 years ago
0
Support bulk connects in `when`?

#727 jkorinth opened 7 years ago
0
Uninferrable width on reg after using fromBits

#726 da-steve101 opened 7 years ago
0
Q: "make getting-started" fails

#725 omerfirmak closed 7 years ago
3
RegUpdate and RegReset?

#724 cornytrace opened 7 years ago
3
firrtl_interpreter/Concrete.scala: randomSInt produces out of bounds value.

#723 stevenmburns opened 7 years ago
2
Deprecate Fill(Chisel.Data, Int) and generate error in compatibility mode.

#722 ucbjrl closed 7 years ago
0
Remove extraneous apply() from vec.tabulate - #718

#721 ucbjrl closed 7 years ago
0
Add Chisel3 clock methods.

#720 ucbjrl closed 7 years ago
0
Fill(Chisel.UInt, Int) is in Chisel2, but not supported by Chisel3

#719 ucbjrl closed 7 years ago
1
Vec.fill appears to be badly broken

#718 ascenium closed 7 years ago
10
fix the outputlist size

#717 songmaotian opened 7 years ago
3
OrderedDecoupledHWIOTester doesn't report error when compare failed

#716 songmaotian opened 8 years ago
0
Will OrderedDecoupledHWIOTester insert bubble for the output.ready signal?

#715 songmaotian opened 8 years ago
2
Renameiotesters

#714 ucbjrl closed 8 years ago
0
val differs from expression after assignment

#713 pw-gecos opened 8 years ago
0
Return Seq, not Vec, from PriorityEncoderOH

#712 aswaterman closed 8 years ago
0
Use Seq, not Iterable, when order matters

#711 aswaterman closed 8 years ago
0
Chisel3 compatibility: Allow asserts with empty messages

#710 aswaterman closed 8 years ago
0
Verilog doesn't use`else` so memory not inferred as RAM

#709 sclukey opened 8 years ago
2
Update to current sbt resolver idiom.

#708 ucbjrl closed 8 years ago
0
Cautionary Tale -- Chisel/ISE issue

#707 shunshou opened 8 years ago
3
Inconsistent member names in C++ emulator

#706 kenmcmil opened 8 years ago
0
Chisel3compatibilitycheck

#705 ucbjrl closed 8 years ago
1
add package object with new literal creation implicits

#704 chick closed 8 years ago
0
Java Exception (and useless error message) on a Reg of Vec of size 0

#703 ccelio opened 8 years ago
0
Flag to enable warnings for any modules with any unconnected ports

#702 ascenium opened 8 years ago
1
Use of "config" as a Chisel value name results in syntax error in Verilog output

#701 ascenium opened 8 years ago
0