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Hi, big thanks for great project!
I'm trying to get linux with ethernet and sdcard on ac701 board.
My problems with this board was:
1) The board has low voltage on USB-UART CP2103GM. VIO port has …
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Is it possible to geneeate the verilog files for the IPs?
If so, can anyone help me on this regard? I want to generate the verilog design files for the ethernet module that I want to integrate for my…
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Hi,
I'm using DE2-115 board using MII mode. The netboot works fine (LiteX can download bios/linux image from TFTP server) if the board connects to the PC directly. If the board connect to the PC via …
lapnd updated
2 years ago
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Hello, I am stuck by running:
```
python3 mistex_boards/qmtech_xc7a100t_daughterboard.py Menu
```
specifically at the part of building the core in Vivado part, here is my `vivado.log`:
```
…
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We currently don't support LiteX master (as of 2022-08-24), with `dma_test` resulting in an instantaneous reboot, even without a kernel panic (i.e. no crashdump). The 2022-04 tag works, as does the fo…
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I found the https://github.com/enjoy-digital/liteeth/commit/aff1916a039815861f428270e48fe0e4175cc785 breaks my Etherbone communication, where I do not wish the board to receive broadcast packets anywa…
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I would like to use the LiteEth core as a standalone core within my designs. I'm using the Versa ECP5-5G board as my development platform. This repository contains a gen.py file that exists to perform…
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**Describe the bug**
When I try to build the example app `samples/hello_world` for the `litex_vexriscv` board in a clean zephyr project with:
`cat overlay.config | xargs west build -b litex_vexriscv…
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The removal of `jtag_atlantic` seems to have been premature, given neither `nios2-terminal` not `litex_term` are able to connect to the JTAG UART synthesised by passing `--uart-name jtag_uart` when bu…
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I must be missing something truly elementary. When I run `gen.py` with something like the following yml:
```
phy: LiteEthPHYMII
vendor: xilinx
clk_freq: 100e6
core: wishbone
…