-
Hi,
I installed openram in Mint 20.3 using pip3 (openram python files wwere deployed to my HOME folder in /home/myusername/.local/lib/python3.8/site-packages/openram ).
Then, I a simple config fil…
-
I'm trying to compile a 1Kb x 8 bit SRAM using the scn3me_subm technology, but I got an "import CellProperties" error (works ok with the scn4m_subm technology though! ). Here's the log and config file…
-
Hi,
I'm trying to generate a 1Kbyte (1024 words x 8bit x 1bank x 1port) SRAM using sky130, but openram complains about it with a pin iterator/pin not found error. Here's the log and my config file
…
-
## Expected Behavior
* You are able to use Xyce for doing analog spice simulations inside the skywater-pdk
## Actual Behavior
* It doesn't work
## Comments
I'm creating this bug to tr…
-
Hi,
I was using OpenRAM for the first time, trying to generate an SRAM of 256kb size with FreePDK45 technology. It's already been running for 40 hours and still has not finished yet. Does it always…
-
I'm trying to generate an sram with custom bit cells. The bit cells are 6T with two word lines, one connected to the left transistor and another connected to the right transistor. The way I implemente…
-
Is it in the current version possible to create a SRAM with more then one bank? I already tried to add "num_banks = 2" to my "myconfig.py" file. But this always results in a layout with only one bank.…
-
**Describe the bug**
A clear and concise description of what the bug is.
I am generating a dual port (1r1w) SRAM with sky130 pdk. An error saying "ERROR: file router.py: line 702: No pins overlapped…
-
Hi, for below configuration file(no of ports=1), I am getting issue('Should use a pin iterator since more than one pin vpb' and 'No pin found with name vpb on sky130_fd_bd_sram__sram_sp_colenda. Sa…
-
**Describe the bug**
A clear and concise description of what the bug is.
**Version**
Which commit are you using?
**To Reproduce**
What did you do to demonstrate the bug?
Please include your …