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参考 [教程](https://github.com/openjdk-riscv/jdk11u/wiki/SPECjvm2008-Benchmark) 方法，开始测试jdk8
当前报错
```
zhangxiang@k9-plct:~/rv32/SPECjvm$ /home/zhangxiang/rv-jdk8u/jdk8u/build/linux-riscv64-normal-core…
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```
__attribute__((noipa))
void test(long long expr, long long *llp) {
*llp = expr >> *llp;
}
int main(void) {
long long lgot = 1;
test(1LL
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* [RISC-V toolchain on OSX](https://github.com/riscv/homebrew-riscv) rv64 by default and it doesn't work for picorv32
* to have rv32, please install [riscv-gcc](https://github.com/riscv/homebrew-risc…
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```ERROR: Module `rv32_writeback' referenced in module `rv32' in cell `writeback' does not have a port named 'rvfi_ixl'.```
It seems to not be passing verification with a clean install directory wi…
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previous work on RV32 and RV64
https://delaat.net/rp/2019-2020/p49/report.pdf
https://reverseengineering.stackexchange.com/questions/22558/reversing-a-key-gen-firmware-for-risc-v
Ghidra release…
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I attempted to launch the prebuilt image files:
```shell
./rv_emu --bios linux5.4/fw_jump.bin --kernel linux5.4/Image --rootfs linux5.4/busybox.bin --dts dts/riscv_em.dtb
```
OpenSBI appears as …
jserv updated
2 years ago
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The example shell scripts (e.g. `RUN_RV32_fibonacci.sh`, `RUN_RV64_dhrystone.sh` etc) have CRLF line teminators, when they shouldn't. Using dos2unix sorts this out, but it would be best to not have to…
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Hi,
I am a bit confused by how zbpbo works, so I open this issue. Take `clz` as example,
> RV32: Replaced with CLZ in Zbpbo. RV64: Zpn
Does it mean, in rv32 we generate `clz` when the arch has…
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When running just the F extension for RV64, I thought that it should also pick up the RV32/F tests. All it does is runt he test cases in RV64i_m/F dir.
Am I missing something?
riscof run --con…
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My plan was quickly build RV32 for linux, test different cache features, and study how to write a board for Arria 10 board.
Without any good knowledge of the process, I just copy pasted commands ha…