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Hi,
I am trying to run SweRVolf with FuseSoc as per the instructions given in https://github.com/chipsalliance/Cores-SweRVolf#prerequisites
when i ran `fusesoc run --target=sim swervolf` i notice…
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I just noticed that the SweRV repos were renamed to VeeR. Could we pleeeeeease take the opportunity to not just change from SweRV to VeeR, but also call them VeeR-EH1, VeeR-EL2 and VeeR-EH2 for consis…
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Hi,
I have integrated a target for SweRV El2 on branch 1.0. The core is an industry-standard core and it is great if we have a target to run compliance on that.
If you guys are interested, I can se…
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Hi,
as response to
https://github.com/chipsalliance/Cores-SweRV-EL2/pull/
we had to block WIDTH and UNOPTFLAT warnings as we used verilator 4.020 for cores release.
Seems majority of warnings…
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Example, parsing the Swerv-EH1 core on an i5-9600K 3.7GHz takes about 18 seconds.
I tried generating the valgrind callgrind data, but I gave up waiting after a few minutes. Profiling a smaller design…
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Michael working with Srini on this.
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macro snippets -- add macros for additional functions:
- meca odom new
- swerv odom new
- meca odom update
- swerve odom update
- meca wheel pos
- meca wheel speeds
…
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I have TB code, slamming DUT registers for some simulation shortcuts, but verilator issues MULTIDRIVEN warning for this TB code. ( It also didn't like that the flop state variable had
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I'm trying to create a BLE peripheral that periodically notifies the central of a sensor value and then goes to sleep. I'm noticing that even during the `k_sleep`, there's a significant current draw …
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I was compiling 8 cores cluster design - the process allocated ~139GB memory. the simulation of the same design allocated ~70MB memory.
Is there any way to reduce memory demand during compilation ? …