chipsalliance Cores-VeeR-EH1 issues

chipsalliance / Cores-VeeR-EH1

VeeR EH1 core

Apache License 2.0

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issues

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Make all functions automatic

#126 olofk opened 2 months ago
0
extension `zicsr' required

#125 ahmdotm opened 5 months ago
0
tcl file

#124 ahmdotm opened 5 months ago
0
Has the maintenance of this repository been stopped?

#123 zhangkanqi opened 10 months ago
1
Instruction after pmpaddr0 csr write was not executed

#122 Ankelih closed 11 months ago
7
Not generate waveform when using vcs to test Hello World.

#121 zhangkanqi opened 11 months ago
2
coremark/dhrystone testing can't get 4.9 CM/MHz with rtl simulation or in FPGA

#120 chithize opened 1 year ago
0
Change 'function' into 'function automatic' to fix verilator 5.0 compilation abort

#119 tomverbeure opened 1 year ago
0
The new feature of verilator stops building procession

#118 LoveMyPillow opened 1 year ago
2
OpenOCD download to ICCM/DCCM failed.

#117 cocckkimo closed 1 year ago
1
Blocking Loads/DMA disable

#116 omezrich opened 1 year ago
0
Repo renaming

#115 olofk closed 1 year ago
2
Coremark for new extension

#114 HamzaShabbir517 opened 1 year ago
0
Corected_SRA_Check.svi

#113 aaqibhs76 opened 1 year ago
0
Added support of riscof comliance testing.

#112 akifejaz opened 1 year ago
0
facing issues when C code size goes beyond 8KB

#111 yash-agnisys opened 2 years ago
1
Question about pipeline FF enable signals

#110 tunefish777 opened 2 years ago
0
Fix FuseSoC simulation target

#109 olofk closed 2 years ago
0
Fusesoc's sim target is deprecated

#108 RRozak closed 2 years ago
10
GHR refresh

#107 Zissi-Lei opened 2 years ago
1
Usage scenarios of different DFFs

#106 Zissi-Lei opened 2 years ago
0
Unable to replicate performance improvement achieved by using different target values

#105 samfishman1 opened 2 years ago
1
CoreMark test score

#104 Zissi-Lei closed 2 years ago
2
Try running multi thread program on swerv EH1 core

#103 rajat-agnisys closed 3 years ago
2
openocd timeout occurs when trying to load elf file using command 'load_image'.

#102 nikhill-agnisys closed 3 years ago
7
Remove not existing file from vivado.tcl

#101 kamilrakoczy closed 3 years ago
3
fpga_optimize cannot be set to 0 in swerv_config

#100 jlucnagel opened 3 years ago
1
slip in dec_decode_ctrl

#99 kuangxin closed 3 years ago
0
Timing violations with Vivado

#98 Rusty-Wire closed 3 years ago
4
$readmem file address beyond bounds of array

#97 HamzaShabbir517 closed 3 years ago
8
GCC version in Makefile

#96 qian-gu closed 3 years ago
4
Formal Verification of SweRV EH1 using riscv-formal

#95 ShashankVM closed 2 years ago
0
Fix FuseSoC config generator

#94 joannabrozek closed 3 years ago
8
Declare variables before using them

#93 tgorochowik closed 3 years ago
1
cmark_dccm fails to build

#92 danielmlynek closed 3 years ago
3
No tags for releases

#91 robtaylor closed 3 years ago
5
tlu_flush_path_e4

#90 kingstone1927 opened 3 years ago
7
Remove unused scan_mode input from dmi_wrapper

#89 olofk closed 3 years ago
0
which unit control flushing of the pipelines?

#88 kingstone1927 closed 3 years ago
3
print instruction to exec.log

#87 kingstone1927 closed 3 years ago
2
Stall point

#86 kingstone1927 closed 3 years ago
5
Delay after fetching instructions when not using icache

#85 crazy-catlady closed 3 years ago
4
Set default mrac value with swerv.config

#84 olofk opened 3 years ago
1
How can I debug using Verilator and gdb

#83 kingstone1927 closed 3 years ago
6
Only load Vivado TCL files when using Vivado

#82 olofk closed 3 years ago
0
Macro definitions not being found

#81 rlb1116 closed 3 years ago
2
Can I integrate the Cores-SweRV on Zedboard fpga?

#80 kingstone1927 closed 3 years ago
1
question about adding custom instructions

#79 feiger313 closed 3 years ago
2
Speculative load observed on LSU AXI

#78 pieter3d closed 4 years ago
10
NMI HELP

#77 Richard2088 closed 3 years ago
1