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In [ctlmgr.py](./artiq/devices/ctlmgr.py), there are two nearly-identical classes ([Controllers](https://github.com/m-labs/artiq/blob/0b43ec4719dd67aa0d839a9e9c69e26783481bdf/artiq/devices/ctlmgr.py#L…
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Comments of @gkasprow front panel designs. They look good!
- [x] Please use EEM code names where possible. Let's keep the amount of text on the front panel to a minimum so it doesn't get over crowd…
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Timestamps for input events, and/or as used in the gater, seem to be deterministically wrong on the ~100 ns level.
Check out this experiment for illustration, which uses a loopback connection (loop…
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Using build 20180530 HMC830 SAWG updatedJESD204B 38b51282226f9. I see no RF output from BaseMod. Things I've checked.
- swapping BaseMod boards
- different Sayma DAC channels
- confirmed that diff…
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The Sinara ecosystem lacks a digital servo capability beyond SU Servo. I am interested to hear what people think might be a good path to creating one. I have laid out a few options.
## Voltage ou…
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If I've understood correctly, @sbourdeauducq believes that we will have issues with the AMC WR implementation, even if both DDMTD inputs are from IOs in the same bank as the helper PLL. This is a prob…
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Using windows 7:
I've been manually fixing this for a while, it occurred for every version at least since 3.0, including 4.0.dev.
Since it is confusing to new users, I thought I should bring it up:
…
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I'm running the SYSU Kasli variant with EEMs TTL and Urukul. Running gateware and firmware version d0f6123f. Relying on internal Kasli internal clock I get an error.
```
device_db = {
"core"…
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@sbourdeauducq I noticed that on the board I got from @hartytp today the ARTIQ starts after several tens of seconds. Another board in my lab behaves in the same way. Other boards start immediately. W…
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_From @kjh-m on October 11, 2018 7:35_
Hello,
I'm getting glitches from AD9912 output during a phase ramp experiment. Phase is ramped by small steps at a given intervals, while keeping the frequen…