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To build a simulation for my verilog mesh I tried this command from the lab:
$ cd sims/verilator
$ make CONFIG=GemminiEE290Lab2RocketConfig
It was an epic bomb :) A lot of messages about deprec…
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The internal application on which I'm working contains 1800 global refs. This results in `GlobalRefOp::verify()` being 64% of the runtime. Drilling in further: each time the verifier runs (1800 times …
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```
circuit Test : %[[
{
"class":"fake",
"target":"~Test|Test/Test:Example"
}
]]
module Example :
module Test :
inst Test of Example
```
When trying to run this test, it…
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This is a proposal for a new API that allows us and others to create new backends for simulations and other purposes.
It is in driven by to RFC #725, which moves chisel-testers functionality into chi…
chick updated
2 years ago
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As discussed here https://github.com/freechipsproject/firrtl/pull/1085#issuecomment-494150560.
**Type of issue**: other enhancement
**What is the use case for changing the behavior?**
**I…
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Consider the following fir.
```scala
circuit Test :
module Test :
input clock: Clock
input a1 : UInt
input a2 : UInt
input a3 : UInt
input a4 : UInt
reg c : …
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In verilog, I can assign Clock is equal to another clock or 1. But I can't assign clock is 1.U in chisel? How can I fix it?
Verilog:
assign clk_IR = ((state_reg == SHIFT_IR)||(state_reg == C…
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Change build.sbt to move to 3.4
Need to redo how verilog and firrtl are printed out in multiple places in test/
e.g., ./src/main/scala/generator/cilk/cilk_for_test06.scala
https://github.com/sfu-a…
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Hello,
I'm a little bit confused about the purpose of `ExpandWhens` pass in Firrtl, which runs before the IR is lowered to HW. It seems to me that it tries to convert a more high-level construct (i…
Kuree updated
2 years ago
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tl;dr: this is a proposal for a "debug mode" which enables specific CIRCT signals to always show up in the output, but also to not block optimizations. This is entirely based off of ideas of and discu…