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For some reason, when I ran `sudo ./litex_setup.py --gcc=riscv` as described in the installation instructions from the README, the script would download the toolchain, extract it and (apparently) do n…
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The description of the **Did you know?** section mentions the use of the `addi` instruction, but the example uses the `add` instruction.
I can't understand how `a0 + a2` is equivalent to `a2 …
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# FreeBSD and RISC-V: The Future of Open Source IoT Ecosystem :: I can I up 🙃 — feng.si
2016 年,我们团队抛弃 Linux,前瞻性地在全美知名物流平台 PkgRun 项目中全线部署 FreeBSD 环境,距今已有整整三个年头。从发布之初的 10.3-RELEASE 一路无缝升级到当前的 12
[http…
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RISC-V Integer Calling Convention in web site:"https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md" says that "Aggregates whose total size is no more than XLEN bits are passed in a…
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https://github.com/zhouyecs/mit_arch_labs
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What FPGA board would be sufficient to do this course?
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The current RISC-V core (from TextBook) may not support these instructions: -
SLL
SLLI
SRA
SRAI
LUI
AUIPC
XOR
XORI
BNE
BLT
BLTU
BGEU
BGE
SLT
SLTI
SLTU
SLTIU
JALR
FENCE…
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I added this as a comment on #502 but think it might have gone unnoticed. Here is another example from the `RISC-V` spec. where `sailcov` gives warnings and produces confusing output:
```
default …
rmn30 updated
2 months ago
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I would like to start a discussion about the need for a method to do a functional equivalency check
between 2 models.
As I've started playing around with the RISC-V Sail model, I can see places w…