-
Hi,
I am working on porting Briey soc to Xilinx fpga board and have issue with sdram so I use simulator to extract reference waveform.
I noticed a regression in briey soc simulation with https://g…
-
It seems that some recent changes broke the build of the vga project:
```bash
VexRiscvSocSoftware/projects/briey/vga$ RISCV_NAME=riscv32-unknown-elf RISCV_PATH=/opt/riscv32i make
/opt/riscv32i/bi…
-
I have a compiler built with `--enable-multilib` flag
so while generating rv32i binaries i use this flag `-march=rv32i` but objdump still generates a dump containing floating point instructions
for…
-
I created the object files with -Og and -g flags to allow debugging
[link.txt](https://github.com/riscv/riscv-gnu-toolchain/files/1367155/link.txt)
-
I am trying to install the RV32I toolchain with the riscv32-unknown-elf- prefix. However, adding `--with-xlen=32` or `--enable-multilib` doesn't seem to work.
`./configure --with-xlen=32 --with-gui…
-
I'm getting the following error when I run the make command:
In file included from /home/sourav/Desktop/HackDAC/ri5cy_gnu_toolchain/build/src/newlib-gcc/gcc/cp/except.c:1023:0:
cfns.gperf: In func…
-
I've been working on implementing la and lla along with %pcrel_hi and %pcrel_lo in llvm and ran into a problem when linking the output. While reducing the test I actually ran into a case where ld wou…
-
Hi @FrancescoConti ,
I ran successfully `cmake_configure.riscv.gcc.sh`.
Then as a next step, I am trying to run `make vcompile`
Here, I am getting below errors.
```
Scanning dependencies of ta…
-
I want to add rv32imaf/ilp32f to the list of multilibs built.
So after I ran through one build of the tools using the GNU MCU Eclipse scripted docker approach I then went to ~/Work/riscv-none-gcc/ris…
-
See patch queue [here](https://reviews.llvm.org/differential/?authors=asb&order=updated).
Status: patches 1-7/10 have reviewed and committed upstream. 8/10 and 10/10 are awaiting review.
* [[RISCV…