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It would be nice to remove the dependencies around the verilog DVI generation.
litevideo already includes a TMDS encoder module that should work in place of the verilog one.
https://github.com/enj…
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I noticed the latest docs show that a simple `@always_comb` block can be converted to a Verilog `assign` statement with a `wire` type for the output: http://docs.myhdl.org/en/latest/manual/conversion_…
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With #8, I think the library will become interesting for a wider audience, now also including VHDL and Verilog users. However, at the moment the name of the library is rather generic. I think it would…
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Seems that the Verilog files are generated from the Python ones instead of being written by hand. I think it would be nice to have them generated in a `gen` folder instead of having both Python source…
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Hi everyone,
I am trying to simulate a design containing some Altera IPs but for all of the IPs GHDL give me a warning `"instance "IP" of component "IP" is not bound"`. So, I just created a PLL and…
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Hello! When using yosys, I found that the results synthesized by the script below are not ideal, so I would like to ask if any seniors can give pointers to the deficiencies of the script below,The res…
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**Type of issue**: bug report
**Other information**
**If the current behavior is a bug, please provide the steps to reproduce the problem:**
Here is an example where a Verilog attribute is bein…
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The core generation for FPGA fails due to:
- [x] Memory initialization is generated only inside the ifndef SYNTHESIS block #4752 - -> Fixed by https://github.com/llvm/circt/issues/4752#issuecommen…
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VPR has had built in support for reordering RR graph nodes to improve cache efficiency since https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/1271.
The existing method reorders nod…
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I don't want to have to install Icarus Verilog just to get this one header file.