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This isn't necessarily a bug, but I do feel it makes Verilog identifiers that Migen generates more difficult to read.
Migen has a tendency to decorate Verilog identifiers with the `__main__` prefix i…
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- Java Formatter
- C++ Formatter
- Verilog
- ASM?
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I'm trying to build this toolchain for Pulpino, unfortunately I get the following problem on several commits. Is there any combination of Pulpino / ri5cy_gnu_toolchain that works?
Here I'm using Ub…
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### Version
Yosys 0.30+48
### On which OS did this happen?
Linux
### Reproduction Steps
Hello,
I have come across an inconsistency problem during the synthesis process while using Y…
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### Version
Yosys 0.30+48
### On which OS did this happen?
Linux
### Reproduction Steps
Hello,
I have come across an inconsistency problem during the synthesis process while using Yosys:
Ver…
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The target UART speed is configured inside the SOC module as 1.000.000 baud. However the real output rate on the UART USB adapter is well below the target value. This is the baud rate setting in SOC.v…
fm4dd updated
9 months ago
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To scale to many-core architecture, the L2 cache ports of Xiangshan core has been modified to support CHI ([Xiangshan-L2-with-CHI-ports](https://github.com/OpenXiangShan/CoupledL2/tree/chi-coupledl2))…
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Good day!
I ran into an issue where Verilator seems to evaluate a three-way single-bit XOR expression incorrectly. I have seen #4709 which could be related, but it is not obvious to me that this is…
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If I want to jump back from the
### Hardware Description Languages
section,
is there a way to get the FOMU back to the configuration needed for the
### Python on FOMU
or
### FOMU as a CPU
…
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Currently the verilog for commonlib.MuxN is generated like the following:
```
module commonlib_muxn__N2__width9 (
input [8:0] in_data [1:0],
input [0:0] in_sel,
output [8:0] out
);…