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Environment:
- Xilinx Alveo U200 Data Center FPGA Acceleration card
- Ubuntu 22.04.4 LTS
- Vitis Unified IDE 2023.2
- gcc version 11.4.0, installed from "sudo apt install build-essential"
- Proje…
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Hi Gabriel,
Thanks for all this info, very good of you, but I have a slight issue:
The process runs through fine, but when I burnt the output/Zybo-Z7-20-3.0.1.img to a card, try to boot, nothing…
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I have questions about Vitis Model Composer.
- Is Sysgen rebranded to Vitis Model Composer, or are they 2 different products?
- Will HDL-Coder work with Vitis Model Composer / is it necessary?
- …
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## Issue Description ##
I created the project in windows, and after a lot of IPs were passed, an error was suddenly reported.( I followed the build_instructions in the zip file.)
## Setup Detail…
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Hi, Alex,
I am trying to port PCIe example project to [BOE board](https://github.com/hpb-project/BOE) v1.1, which is based on Xilinx zu7cg FPGA. It seems that the most similar board is ZCU106 (i.e.…
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## Prerequisites
Possible Bug in the current version v0.10 of FINN.
## Quick summary
Ipgen step for the threshold hls layers in the latest version of finn (v0.10) fails. The stack trace is inclu…
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I tried to compile with `iverilog` the following code:
```
localparam InCnt = 4;
localparam CntWdt = 16;
reg [CntWdt-1:0] count [InCnt-1:0];
......
always@(count) begin
......
```
and I…
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I have few friends that were taking this 369, and it seems this course is a complete dog shit.
My friends had to re-take the course the second time to pass after failing this PoS course.
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Hi,
"ERROR: [IMPL 213-28] Failed to generate IP.
command ‘ap_source’ returned error code"
This error occurs when using HLS to synthesize “Example2: lstm autoencoder targeting anomaly detection”…
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Hey -
I am attempting to build a schematic diagram visualizer tool for UHDM designs. To keep the scope small, layout of individual components is decided to be out of scope, at least for now. Howeve…