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What should be included in the next update of the coredistools library (used for x86/x64 GC stress, R2RDump disassembly, superpmi asm diffs, RyuJIT "late disassembler", ILC (?), and possibly more)?
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At the moment 32bit android arm is not supported, so the fallback without SIMD is required.
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Encountering an ICE after removing NEON preference in `useSVEForFixedLengthVectors` for 128-bit vector register size SVE code generation.
Context:
There's currently a `>= 256` vector size restrict…
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|--------------------|----|
| Bugzilla Link | [PR48016](https://bugs.llvm.org/show_bug.cgi?id=48016) |
| Status | NEW |
| Importance | P enhancemen…
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Hi vectorscan team:
I am trying to build vectorscan on several ARM 32 platform, such as armv7-a and cortex-a7 or cortex-a15, but I encountered the following errors:
> /mnt/openwrt/build_dir/targ…
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I'm trying to compile Highway 1.0.3 with [EasyBuild](https://easybuild.io) using the following recipe: https://github.com/easybuilders/easybuild-easyconfigs/blob/develop/easybuild/easyconfigs/h/Highwa…
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Using the latest cpufetch v1.06, the program builds fine, but then crashes when ran on aarch64.
Debugging with Valgrind led me to find two off-by-one errors:
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Commit 1b746bc67d58a6f3172334…
suve updated
2 months ago
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There is nearly no space for information:
```
[marcin@sbc ~]$ /tmp/cpufetch
SoC: Rockchip
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The current method of generating decode/encode functions based on the `codec.txt` bitmap format has limitations in terms of:
- Flexibility when specifying instruction aliases and variants, e.g. `DC` …
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```csharp
namespace System.Runtime.Intrinsics.Arm
/// VectorT Summary
public abstract class Sve : AdvSimd /// Feature: FEAT_SVE2 Category: counting
{
/// T: [uint, int], [ulong, long]
p…
a74nh updated
3 months ago