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Shouldn't it be `counter_test/counter.v`?
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This may be related to Issue #1400.
This is seen in testing for PR #1515 , the xc7\_vendor tests.
I see the Issue #1400 failure for test bram\_sdp\_test\_36 for Basys3.
Later I see other fail…
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I set the toolchian to the Basys3.config. but when i click the menu basys3-export vhdl&start vivado
it remind me : cannot run program "vivado",createProcess error=2.
win10
vivado2015
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## Steps to reproduce the issue
[test.zip](https://github.com/YosysHQ/yosys/files/4503542/test.zip)
The `test.zip` archive contains a test design and the tcl synthesis script.
Reproduce:
1. …
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can the MIPS CPU example be downloaded to the basys3 ?
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I have noticed that Digital's MUXes give me a consistent error message no matter how I set them up.
It goes as follows:
For 8 bit mUX: "There are 8 bits needed, but one bit is found"
For 4 bit mUX:…
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is it possible to generate a .tcl file?
i want to generate a bit file by click menu and use
`vivado -mode batch -source autobit.tcl`
how to transfer the var to the file content?
autobit.tc…
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See following assertion when make vivado target for xc7/buttons_basys
Did not see from other tests. Suspect errors for wire "SW6END0"
```
Traceback (most recent call last):
File "/home/yangf…
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With https://github.com/verilog-to-routing/vtr-verilog-to-routing/pull/969, in theory fasm2v should have no differences with Vivado, except for bugs in either synth or fasm2v.
Targets that are pass…
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when running `make all_xc7 -j40` the tests fail with:
```
SBY 10:55:55 [ff_ce_sr_17_fdpe_proof] Removing direcory 'ff_ce_sr_17_fdpe_proof'. …