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### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have up…
ftab updated
4 months ago
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### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have updat…
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### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have up…
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Continuing Issue #661
After force recreating thumbnails for all ETDs, #685, manually create thumbnails of ETDs where the title or cover page is not the first page.
Create thumbnail of page 1:
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### Description
A vcs time profile for chip_sw_pwrmgr_smoketest shows 50% of the time is spent in uvm_hdl_deposit for mem_bkdr_util::write. This is excessive, and we should be able to reduce it signi…
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I have VUnit installed in WSL2 and Modelsim intel edition in windows 10.
I set VUNIT_SIMULATOR and VUNIT_MODELSIM_PATH in **etc/enviroment** and **etc/profile** and **~/.bashrc** to:
`VUNIT_SIMUL…
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Hi,@koide3,
When I run " roslaunch hdl_people_tracking hdl_people_tracking.launch ",the following error occurs.
... logging to /home/jintaiyu/.ros/log/9cdcaf3c-f88f-11e8-b306-000ec6a10ce2/roslau…
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It is an enhancement request.
VHDL is supported, but Verilog HDL is not.
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Hi there,
I am using the Cologne Chip toolchain `p_r` for timing analysis with [PipelineC](https://github.com/JulianKemmerer/PipelineC). Specifically, what I am doing requires knowing the the FMAX …
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#### Feature request description
Currently Sourcegraph doesn't support syntax highlighting for Verilog and VHDL.
![image](https://user-images.githubusercontent.com/94965293/143841769-5fb4e571-1ae…