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chili-chips-ba
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openCologne
Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples. https://www.chili-chips.xyz/open-cologne
https://nlnet.nl/project/openCologne
BSD 3-Clause "New" or "Revised" License
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PCB PMOD Request: USB2.0 PHY (usbIO)
#43
chili-chips-ba
opened
2 weeks ago
1
PCB PMOD Request: An array of Power Transistors (pwrIO)
#42
chili-chips-ba
opened
2 weeks ago
8
PCB PMOD Request: Quadrature Encoder For Educational Use
#41
chili-chips-ba
closed
2 weeks ago
3
PCB PMOD Request: Realtime clock with PWR switch (tmrIO)
#40
chili-chips-ba
opened
2 weeks ago
0
Can the QSPI pins and ConfigFlash be repurposed for User App?!
#39
chili-chips-ba
closed
1 month ago
2
Constraints-driven P_R?!
#38
chili-chips-ba
opened
1 month ago
0
L2T4 logic funcion gaps compared to standard LUT4?!
#37
chili-chips-ba
opened
1 month ago
0
P&R Error: ERangeError when connecting BUFG to user logic in GateMate FPGA
#36
harunkovacevic
closed
2 months ago
9
P_R '-om' default is set agressively and does not match Olimex default
#35
chili-chips-ba
closed
1 month ago
1
Out of context / Virtual Pin Support
#34
JulianKemmerer
opened
2 months ago
4
WANTED: IOSERDES for GateMate
#33
chili-chips-ba
opened
2 months ago
0
Issue with using sv2v for a simple Blinky example
#32
TarikHamedovic
closed
2 months ago
1
No warning issued for unconstrained ports
#31
tarik-ibrahimovic
opened
3 months ago
5
Mismatch in post-PnR sim and chip operation
#30
tarik-ibrahimovic
opened
3 months ago
3
Error When Adding synth_gatemate Command in CDC Workflow
#29
TarikHamedovic
closed
2 months ago
5
LUTRAM for CologneChip?!
#28
chili-chips
closed
1 month ago
13
Error 10 on simple keyboard module
#27
goran-mahovlic
closed
2 months ago
9
Validation and introduction of CDC Linter into project QA workflow
#26
chili-chips-ba
closed
2 months ago
24
Undefined behavior in synthesis depending on the bit width of variables
#25
tarik-ibrahimovic
opened
4 months ago
17
GHDL-YOSYS-PLUGIN error: cannot find "std" library
#24
TarikHamedovic
closed
3 months ago
1
Error in GateMate p_r tool inferring CC_MULT
#23
aimamovic6
closed
1 month ago
20
GateMate simulation quirks and problems
#22
chili-chips-ba
closed
2 months ago
4
FATAL ERROR in GateMate p_r Tools for OPL3 FM Synthesizer
#21
TarikHamedovic
closed
3 months ago
6
Issue with inout port of constraint file
#20
TarikHamedovic
closed
4 months ago
6
Issue with ILA using Olimex GateMate board
#19
TarikHamedovic
closed
3 months ago
9
Timing constraints and 'report_timing' in CologneChip proprietary PNR?!
#18
chili-chips-ba
closed
1 month ago
10
Improper UART synthesis
#17
tarik-ibrahimovic
closed
4 months ago
15
OPL3 FM Synthesizer Synthesis and Simulation Issues
#16
TarikHamedovic
closed
2 months ago
33
PCB Feature Request: Basic IO expander for Onlimex (simpleIO)
#15
goran-mahovlic
closed
1 month ago
2
CC_PLL Verilog simulation model bug
#14
tarik-ibrahimovic
closed
4 months ago
4
GateMate Yosys in the CologneChip tool package is outdated
#13
chili-chips-ba
closed
2 months ago
1
PCB Feature Request: Plug-and-Play compatibility of ULX5M FPGA pinout to Olimex
#12
chili-chips-ba
opened
5 months ago
1
UART Receiver and Transmitter Not Functioning on Olimex GateMate Board
#11
TarikHamedovic
closed
5 months ago
2
GateMate Constraint File Pin Declaration Format
#10
TarikHamedovic
closed
4 months ago
7
PCB Feature Request: Provide 3.5mm Audio Jacks (joyIO)
#9
chili-chips-ba
closed
2 weeks ago
2
GateMate - Verilator relationship
#8
chili-chips-ba
closed
2 months ago
2
GateMate pre-packaged downloader does not work with Olimex board
#7
chili-chips-ba
closed
4 months ago
4
PCB Request: eduIO
#6
chili-chips-ba
opened
5 months ago
9
PCB PMOD Request: Low-noise 50MHz+ multi-channel OpAmp (anaIO)
#5
chili-chips-ba
opened
5 months ago
2
PCB Feature Request: Provision hooks for per-rail current measurements
#4
chili-chips-ba
closed
2 weeks ago
2
GateMate SystemVerilog support
#3
TarikHamedovic
closed
2 months ago
28
Error after trying to build Yosys for Linux
#2
harunkovacevic
closed
6 months ago
1
1.Blinky 'make_impl' command gives 'FATAL ERROR: Input CLK_REF of net 86 must have dedicated CLK pin connection'
#1
TarikHamedovic
closed
6 months ago
1