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chili-chips-ba
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openCologne
Spicing up the first and only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples.
https://www.chili-chips.xyz/open-cologne
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Improper UART synthesis
#17
tarik-ibrahimovic
opened
1 week ago
6
OPL3 FM Synthesizer Synthesis and Simulation Issues
#16
TarikHamedovic
opened
2 weeks ago
1
Simple IO expander for Onlimex Misc connector
#15
goran-mahovlic
opened
2 weeks ago
1
CC_PLL Verilog simulation model bug
#14
tarik-ibrahimovic
opened
2 weeks ago
1
GateMate Yosys in the CologneChip tool package is desperately outdated
#13
chili-chips-ba
opened
2 weeks ago
0
PCB Feature Request: Plug-and-Play compatibility of ULX5M FPGA pinout to Olimex
#12
chili-chips-ba
opened
2 weeks ago
0
UART Receiver and Transmitter Not Functioning on Olimex GateMate Board
#11
TarikHamedovic
closed
2 weeks ago
2
GateMate Constraint File Pin Declaration Format
#10
TarikHamedovic
opened
2 weeks ago
3
PCB Feature Request: Provide 3.5mm Audio Jacks
#9
chili-chips-ba
opened
2 weeks ago
0
GateMate - Verilator relationship
#8
chili-chips-ba
opened
2 weeks ago
0
GateMate pre-packaged downloader does not work with Olimex board
#7
chili-chips-ba
opened
2 weeks ago
2
PCB Feature Request: Provide sufficient number of LEDs and Push-Buttons, via 1-Wire GPIO expander
#6
chili-chips-ba
opened
2 weeks ago
0
PCB Feature Request: Provide good dual analog OpAmp
#5
chili-chips-ba
opened
2 weeks ago
0
PCB Feature Request: Provision hooks for per-rail current measurements
#4
chili-chips-ba
opened
2 weeks ago
0
GateMate SystemVerilog support
#3
TarikHamedovic
opened
1 month ago
25
Error after trying to build Yosys for Linux
#2
harunkovacevic
closed
1 month ago
1
1.Blinky 'make_impl' command gives 'FATAL ERROR: Input CLK_REF of net 86 must have dedicated CLK pin connection'
#1
TarikHamedovic
closed
1 month ago
1