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**Describe the bug**
When using the AXI-Lite top-level interface, Vivado 2023.2 produces critical warnings like this for the AXI Stream interfaces for SLINK:
[BD 41-967] AXI interface pin /process…
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### Resource Title
NEORV32
### Resource Description
A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independe…
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**Describe the bug**
It looks like there is a duplicate driver for the s1_axis_tvalid_int signal in the neorv32_SystemTop_axi4lite.vhd top-level file:
```
s1_axis_tvalid_int
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Dear Admin,
**Describe the bug**
When I send neorv32_exe.bin file on Tera Term , I receive a notification of ERR_EXE
Tried other examples but the result is still the same
**To Reproduce**
``…
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Hi @stnolting
I'm having problems with SLINK.
The same design in V1.9.5 works and from v1.9.5.5 onwards it doesn't work.
The design is a multiplier added with NEORV32 via SLINK. The FPGA is a…
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**Is your feature request related to a problem? Please describe.**
A clear and concise description of what the problem is. Ex. I'm always frustrated when [...]
**Describe the solution you'd like**…
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Hi!
I am trying to implement the neorv32 core using LiberoSoC for Microsemi FPGAs. Due to the extreme low amount of physical resources available, I need to lower the DMEM and IMEM sizes (I am trying …
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In a very custom version of the processor I am (_mis_)using the [Smcsrind](https://github.com/riscv/riscv-indirect-csr-access) ISA extension to add further CPU-local hardware accelerators. Even though…
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**Describe the bug**
I am using the SLINK interface to feed data into the NEORV32 from a Xilinx AXI DMA core. The SLINK RX FIFO size is set to 16 currently. There are some cases where I end up feedin…
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Hi,
First of all, thank you for your high-quality work on this project. This is a great way to learn VHDL, and CPU architecture.
I am trying to implement the NeoRV32 Core into the OrangeCrab r2…