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neorv32
:rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
https://neorv32.org
BSD 3-Clause "New" or "Revised" License
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Capture variable value in simulation
#906
mahdi259
closed
1 day ago
5
[FPU] prevent GCC from emitting fused multiply-add instructions
#905
stnolting
closed
1 day ago
0
Add COE and MEM file generator options
#904
stnolting
closed
3 days ago
0
Update neorv32_sdi.vhd - Minor typo correction
#903
ucycg
closed
3 days ago
2
Add back Dhrystone port
#901
stnolting
closed
5 days ago
0
Cleanup SW library
#900
stnolting
closed
6 days ago
0
Latency measurement through `CSR(MCYCLE)` adds one extra cycle
#897
Unike267
closed
4 days ago
8
Add NEORV32 as Vivado IP
#894
stnolting
closed
2 weeks ago
0
Unexpected external Interrupt/ XIRQ behavior in Indirect Boot from SPI Flash
#893
ucycg
closed
1 week ago
8
VUnit simulation failure
#892
DatNguyen97-VN
opened
2 weeks ago
1
Fix UART receiver
#891
Unike267
closed
2 weeks ago
1
[bug] uart issue after #883 upd
#890
Polaris-III
closed
2 weeks ago
5
minor rtl cleanups
#889
stnolting
closed
2 weeks ago
0
Extra latency in the first `for` iteration
#888
Unike267
closed
1 week ago
15
[rtl] fix single-step halting
#887
stnolting
closed
3 weeks ago
0
Not immediately halting when single-stepping into an exception
#885
stnolting
closed
3 weeks ago
0
Neorv32 synthesis in Design compiler
#884
mahdi259
closed
3 weeks ago
8
minor rtl fixes
#883
stnolting
closed
3 weeks ago
0
fix external debug-halt vs. exception concurrency
#882
stnolting
closed
3 weeks ago
1
rtl logic optimization and cleanups
#880
stnolting
closed
4 weeks ago
0
JTAG halt request gets missed if it occures during an illegal instruction
#879
mikaelsky
closed
3 weeks ago
5
ASIC Processor boot conccept
#878
ucycg
closed
1 month ago
13
[DMA] use FIRQ select instead of FIRQ mask
#877
stnolting
closed
1 month ago
0
:warning: simplify XBUS gateway
#876
stnolting
closed
1 month ago
0
:warning: rename SLINK data interface registers
#874
stnolting
closed
1 month ago
0
use simplified VHDL file headers
#873
stnolting
closed
1 month ago
0
minor rtl clean-ups and optimization
#872
stnolting
closed
1 month ago
0
Add AXI stream routing?!
#871
stnolting
opened
1 month ago
0
add additional SPI and SDI interrupt conditions
#870
stnolting
closed
1 month ago
0
B ISA extensions only contains Zba + Zbb + Zbs
#869
stnolting
closed
1 month ago
0
[SLINK] split interrupt into two FIRQs
#868
stnolting
closed
1 month ago
0
add back TWI clock stretching option
#867
stnolting
closed
1 month ago
5
A question on simple testbech
#866
mahdi259
closed
1 month ago
6
:warning: rework TWI module
#865
stnolting
closed
1 month ago
3
:bug: fix DMA fence flag, :warning: rework CPU FIRQs
#864
stnolting
closed
1 month ago
0
Support tool-specific standard flags in makefile
#862
jpf91
closed
1 month ago
4
[feature request] Combining SPI and DMA
#861
jpf91
opened
1 month ago
7
:warning: rework TWI interrupt
#860
stnolting
closed
1 month ago
0
:warning: rework ONEWIRE and GPTMR interrupts
#859
stnolting
closed
1 month ago
0
:warning: remove WDT + TRNG interrupts; :bug: fix bug in core-complex clocking during sleep
#858
stnolting
closed
1 month ago
0
CPU RTL optimization
#857
stnolting
closed
1 month ago
0
[feature request] Makefile: Additional CXX_USER_FLAGS only for C++ Compilation
#856
jpf91
closed
1 month ago
3
Update CFU example: use XTEA as "real world" demo application
#855
stnolting
closed
2 months ago
0
Connected SPI bus to on-board Flash and SPI peripheral
#854
lovelesh-mis
closed
2 months ago
1
rework cache system
#853
stnolting
closed
2 months ago
0
[litex] update core complex wrapper
#852
stnolting
closed
2 months ago
0
Minor cache updates
#851
stnolting
closed
2 months ago
0
:warning: processor configuration edits / clean-ups
#850
stnolting
closed
2 months ago
0
✨ Add optional external bus interface cache (XCACHE)
#849
stnolting
closed
2 months ago
0
Changing name of memory size variables
#848
mahdi259
closed
2 months ago
4
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